Computer composed of LS
1. Multiple choice questions
1. A certain byte sequence is 90 EA 37 58 00, which means ()
A. One instruction
B. A string of pixels in the image
C. Data used in calculation
D. All of the above are possible
2. Assuming that an operand of an instruction uses one-time indirect addressing, the address code given in the instruction is 2222H, the content of address 2222H is 4444H, the content of address 4444H is 6666H, and the content of address 66666H Is 8888H, then the operand is ().
A、8888H
B、6666H
C、4444H
D、2222H
3. In the description of von Neumann structure computer instructions and data representation, the correct one is <).
A. Instructions and data are stored in binary form
B. Instructions are stored in binary form, and data are stored in decimal form
C. Instructions and data can be distinguished in form
D. Instructions and data are stored in decimal form
4. Assuming that the computer adopts byte addressing, little-endian, the address of x in a certain variable is FFFF C000H, x=AABB CCDD H, then the content stored in the memory unit FFFF C001H is ().
A.AAH
B. BBH
C. CCH
D. DDH
5. The following is the description of the quick table, the error is ()
A. The English abbreviation of the quick table is TLB. It is called the conversion backup buffer
B. The quick table stores the common page table entries of the current process
C. When hit in the quick table, it must hit in the L1 cache
D. The fast table is a kind of cache, which must be in the CPU
6. The following codes are often used in computers to represent data. Among them, the code with the same ±0 code is ()
I. Original code I. Inverse code III. Complement code IV shift code
A 、 I 和 IV
B 、 II 和 III
C, I and III
D 、 III 和 IV
7. The instruction pipeline of a computer consists of 4 functional segments. The time for the instruction to flow through each functional segment (ignoring the buffering time of the pipeline register between each functional segment) is 50ns, 60ns, 70ns, 40ms, then the computer's The CPU clock cycle is at least ().
A.220ns
B. 70ns
C.40ns
D. 55ns
8. Both the open interrupt and close interrupt operations are used to set ().
A. Interrupt mask register
B. Interrupt enable trigger
C. Interrupt request register
D. Interrupt inward register
9. In the following description of RISC characteristics, the error is ()
A. Regular instruction format, few addressing modes
B. Adopt hard-wired control and command pipeline
C. The operands of arithmetic instructions are not fetched
D. There are not many general registers configured
10. Under normal circumstances, the following () components are not included in the central processing unit (CPU) chip
A, ALU
B. Controller
C. Register
D、DRAM
11. Compared with the microprogram controller, the characteristic of the hard-wired controller is ().
A. The instruction execution speed is slow, and the instruction function modification and expansion are easy
B. The instruction execution speed is slow, and it is difficult to modify and expand the instruction function
C. The instruction execution speed is fast, and the instruction function modification and expansion are easy
D. The instruction execution speed is fast, and it is difficult to modify and expand the instruction function
12. The following is a description of branch prediction:
①Branch prediction technology can be used for control hazard and data hazard processing.
②When using static prediction technology, the prediction result is always the same every time
⑤Under normal circumstances, dynamic prediction has a higher success rate than static prediction
④Instructions that have been erroneously taken to the pipeline for execution when the prediction is wrong must be washed away
In the above description, the correct one is ().
A、①、②、③
B、①、②、④
C、②、③、④
D, all
13. In the following description of the instruction pipeline design, the error is ()
A. Each sub-function during the execution of the instruction must be included in a certain pipeline
B. All sub-functions must pass through the flow section in a certain order
C. Although the actual time used by each sub-function may be different, the time passing through each flow segment is the same
D. It is impossible for the functional components of each pipeline stage to perform non-operations at any time
14. Assuming that the operating frequency of a synchronous bus is 33MHz, there are 32-bit data lines in the bus, and each bus clock transmits data once, the maximum data transfer rate of the bus is ().
At MB 66MB / s
B、132MB/s
C、528MB/s
D、1056MB/s
15. In the following description of RAID technology, the error is ().
A. RAID technology can realize a nautical backup storage system
B. RAID technology can improve the reliability of the storage system
C. The parity information in RAID is stored on one disk
D. RAID improves speed by accessing multiple disks in parallel
16. Start a DMA transfer, the peripheral and the host will complete a () data transfer
A, byte B, word C, bus width D, data block ↵
17. In the memory layered architecture, the order of memory speed from fastest to slowest is ()
A, register-main memory-cache-auxiliary memory
B, register-main memory-auxiliary memory-cache
C, register- cache-auxiliary memory-main memory
D, register-cache-main memory-auxiliary memory
18. Assuming that an operand of an instruction uses one-time indirect addressing, the address code given in the instruction is 1200H, the content in address 1200H is 12FCH, the content in address 12FCH is 38B8H, and the content in address 38B8H is 88F9H , Then the operand is ()
A, 1200H
B, 12FCH
C, 38B8H
D, 88F9He
19. Associative memory is the memory that is accessed by pressing (). ()
A, address specification method
B, content specification method
C, stack access method
D, queue access method
21. In the computer system hierarchy, the interface between hardware and software is ()↵
A, instruction system B, assembly language C, operating system D, compilation system ↵
22. In a bus transaction, the master device only needs to give a first address, and the slave device can read or write multiple data from several consecutive units starting from the first address. This type of bus transaction is called ()
A. Serial transmission B. Synchronous transmission c. Parallel transmission D. Burst transmission
23. Among the following memories, the ones that need to be refreshed periodically during work are ()
A.FLASH
B.SRAM
c.ROM
D.SDRAM
24. In general computer systems, Western character encoding generally uses ()
A. BCD code
B. CRC code
c.ASCII code
D. Gray code'
25. The following is a description of the DMA mode, the error is ()
①. The DMA controller requests the CPU to use the right to use the bus.
②. The DMA method can be used for keyboard and mouse data input.
③ The whole work/0 in DMA mode The process does not require CPU intervention at all.
DMA mode requires interrupt processing for auxiliary operations
A.①.
B.②.③
c.② ④
D.③ ④