ARM cp15 coprocessor operating i-cache

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The format of the MRC instruction is:

MRC{condition} Coprocessor code, coprocessor opcode 1, destination register, source register 1, source register 2, coprocessor opcode 2.
The MRC instruction is used to transfer the data in the coprocessor register to the ARM processor register. If the coprocessor cannot successfully complete the operation, an undefined instruction exception is generated. Among them, coprocessor opcode 1 and coprocessor opcode 2 are the operations to be performed by the coprocessor, the destination register is the register of the ARM processor, and the source register 1 and source register 2 are the registers of the coprocessor.
Instruction example:
MRC P3, 3, R0, C4, C5, 6; This instruction transfers the data in the register of the coprocessor P3 to the ARM processor register. Another
example:
mrc p15,0,r0,c1, c0,0; transfer the data in the register of the coprocessor p15 to the register r0 of the ARM processor, where 1 is the coprocessor opcode 1,0 is the coprocessor opcode 2, and c1 stores the first operand Coprocessor register, c0 stores the coprocessor register of the second operand
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The format of the MCR instruction is:

MCR{condition} Coprocessor code, coprocessor opcode 1, source register, destination register 1, destination register 2, coprocessor opcode 2.
The MCR instruction is used to transfer the data in the ARM processor register to the coprocessor register. If the coprocessor cannot successfully complete the operation, an undefined instruction exception is generated. Among them, coprocessor opcode 1 and coprocessor opcode 2 are the operations to be performed by the coprocessor, the source register is the register of the ARM processor, and the destination register 1 and destination register 2 are the registers of the coprocessor.
Instruction example:
MCR P3, 3, R0, C4, C5, 6; this instruction transfers the data in ARM processor register R0 to the coprocessor P3 register C4 and C5.

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