The program simply receives the data sent from the computer's serial port, and then sends the received data to the computer. It can be sent by serial port monitoring software on the computer. After sending, observe whether there is data received.
The sending module and the receiving module are the same as the previous ones. I won’t post the code here. Just modify the top-level file.
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下面是顶层文件
`timescale 1ns/1ps
module top(clk, Rest_n,uart_rx, uart_tx) ;
input clk;
input Rest_n;
input uart_rx;
output uart_tx;
//wire tx_done;
wire [7:0] data_recv;
wire rx_done;
rs232_rx_cnt u3(
.clk(clk),
.rst_n(Rest_n),
.sel_bps(3'd2),
.uart_rx(uart_rx),
.rx_done(rx_done),
.data_recv(data_recv)
);
rs232_tx_cnt u2(
.Clk(clk),
.rst_n(Rest_n),
.en_go(rx_done),
.tx_done(),
.sel_bps(3'd2),//
.Data(data_recv),
.uart_tx(uart_tx)
);
endmodule
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compiling, downloading the bit file to fpga. 
The above is that the serial port is sending data, 01020304 and so on. In the receiving window part, the sent data is received. The program functions normally.
Attach the pin constraint file. This is vivado. If it is ISE software, the syntax is different.
#set UnusedPin
#set_property BITSTREAM.CONFIG.UNUSEDPIN Pullnone [current_design]
set_property PACKAGE_PIN Y18 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property PACKAGE_PIN F15 [get_ports Rest_n]
set_property IOSTANDARD LVCMOS33 [get_ports Rest_n]
#uart_tx
set_property PACKAGE_PIN M15 [get_ports uart_tx]
set_property IOSTANDARD LVCMOS33 [get_ports uart_tx]
set_property PACKAGE_PIN J20 [get_ports uart_rx]
set_property IOSTANDARD LVCMOS33 [get_ports uart_rx]