LKT chip interface debugging suggestion-IIC interface

This article mainly introduces the problems that need to be paid attention to when using STM32 chip IO simulation mode to debug IIC interface LKT encryption chip. Some people may say that I have operated the XXXX IIC interface chip before, and there is nothing to introduce about the IIC interface. In fact, if the IO simulation IIC program is not well written, it may cause the program to have poor compatibility with individual chips, or the communication will become unstable after a slight adjustment of the communication speed.
Basic introduction-IO port open-drain output:
The figure below shows the structure of the open-drain mode. The '0' on the output register turns off the N-MOS activation and the P-MOS. At this time, the I/O pin is equivalent to connecting to VSS. The '1' on the output register turns off the P-MOS and N-MOS, and the I/O is in a high impedance state. Therefore, a pull-up resistor needs to be added when outputting a high level in open-drain mode.

Debugging notes:
The SDA and SCL lines of the STM32 operating LKT encryption chip must be set to open-drain output, and remember not to use push-pull output.
When STM32 is sending and reading data, the SDA data line pin does not need to be input and output settings, just read the port register status directly.
When STM32 is reading data, when SCL is pulled high, do not perform subsequent operations after a simple fixed delay. Try to make a high timeout judgment (because there is the possibility of the bus being occupied by the slave device, a timeout judgment can be made here If the SCL timeout has not been pulled high, it is considered to be a bus abnormality. This is also in line with the hardware IIC operation logic and more in line with the timing rules.