In early development, the PCIe originally called the HSI (high-speed interconnect), and prior to finalizing its PCI-SIG name PCI Express, to change its name to 3GIO (third generation I / O). Named Arapahoe Working Group (AWG) of the technical working group developed the standard. For the first draft, the ad hoc working group includes only Intel engineers; then expand the ad hoc working group to include industry partners.
PCI Express is a continuous development and improvement of technology.
As of 2013, PCI Express version 4 has been drafted, is expected in 2017 will reach final specification. In the 2016 annual developer conference on the PCI SIG and Intel Developer Forum, Synopsys demonstrated a system running on PCIe 4.0, and Mellanox provides an appropriate card.
Note that there is unidirectional bandwidth, two-way speed doubled.
| PCI Express version | Lines of code | Transmission rate | Throughput | |||
| ×1 | ×4 | ×8 | ×16 | |||
| 1.0 | 8b/10b | 2.5GT/s | 250MB/s | 1GB/s | 2GB/s | 4GB/s |
| 2.0 | 8b/10b | 5GT/s | 500MB/s | 2GB/s | 4GB/s | 8GB/s |
| 3.0 | 128b/130b | 8GT/s | 984.6MB/s | 3.938GB/s | 7.877GB/s | 15.754GB/s |
| 4.0 | 128b/130b | 16GT/s | 1.969GB/s | 7.877GB/s | 15.754GB/s | 31.508GB/s |
| 5.0 | 128b/130b | 32 or 25GT/s | 3.9 or 3.08GB/s | 15.8 or 12.3GB/s | 31.5 or 24.6GB/s | 63.0 or 49.2GB/s |
PCIe 1.0a
In 2003, PCI-SIG introduced PCIe 1.0a, each channel data rate is 250 MB / s, a transmission rate of 2.5 gigatransfer per second (GT / s). Transmission rate is expressed as the amount of transmission per second, rather than the number of bits per second, since the transmission amount does not include additional overhead bits throughput; PCIe 1.x using 8b / 10b encoding scheme, resulting in 20% occupancy (= 2/10 ) original channel bandwidth.
PCIe 1.1
In 2005, PCI-SIG introduced PCIe 1.1. This updated specification includes several improvements and clarifications, but is fully compatible with PCI Express 1.0a. Data rates unchanged.
PCIe 2.0
PCI-SIG on January 15, 2007 announced the PCI Express Base 2.0 specification. The PCIe 2.0 standard PCIe 1.0 to 5 GT / s transmission rate doubling the throughput per channel increased from 250 MB / s to 500 MB / s. Thus, lane PCIe connector 32 (× 32) support of 16 GB / s, the total throughput.
PCIe 2.0 and PCIe v1.x motherboard slot card is fully backward compatible. PCIe 2.0 cards usually available bandwidth of PCI Express 1.1 PCIe 1.x backward compatible motherboard. Overall, the design of the graphics card or motherboard v2.0 to v1.1 or v1.0a with another use.
Said PCI-SIG, PCIe 2.0 point improvement over having a data transfer protocol and its software architecture.
Intel's first chipset supports PCIe 2.0 is X38, as of October 21, 2007, a variety of vendors (Abit, Asus, Gigabyte) began shipping. AMD started its AMD 700 series chipset supports PCIe 2.0, nVidia MCP72 from the start. All Intel chipsets, including Intel P35 chipset supports PCIe 1.1 or 1.0a.
Like as 1.x, PCIe 2.0 using 8b / 10b encoding scheme, so that each channel provides 5 GT / s raw data rate of the active 4 Gbit / s the maximum transfer rate.
PCIe 2.1
PCI Express 2.1 (its specification dated March 4, 2009) supports most of the management plan for the full implementation of the PCI Express 3.0, support and troubleshooting systems. But the same speed and PCI Express 2.0. Unfortunately, the increase in the slot to break the power of backward compatibility between PCI Express 2.1 cards and some of the 1.0 / 1.0a older motherboards, but most motherboards have PCI Express 1.1 connector by vendors through practical program provides BIOS update to support backward compatibility with PCIe 2.1.
PCIe 3.0
PCI Express 3.0 specification version 3.0 provides basic after a number of delays in November 2010. In August 2007, PCI-SIG announced that PCI Express 3.0 will be 8 gigabits per second bit rate of speed (GT / s), and backward compatibility with existing PCI Express. Was also announced, PCI Express 3.0 specification will eventually delayed until the second quarter of 2010. PCI Express 3.0 specification enhanced new features include some optimization of signaling and data integrity, including a transmitter and a receiver equalizer, the PLL improvements, clock data recovery, and the current topology supported channel enhancement.
Analysis of PCI-SIG found in the PCI-SIG feasibility interconnect bandwidth extension technical analysis for six months, it was found eight gigabit per second transmission rate may be manufactured in the mainstream silicon process technology, and can be deployed in the existing low-cost materials and infrastructure, while maintaining full compatibility with PCI Express protocol stack (excluding the impact of negligible).
PCI Express 3.0 upgrade encoding scheme from 8b / 10b encoding prior to 128b / 130b, to reduce the bandwidth overhead from PCI Express 20% 2.0 to about 1.54% (= 2/130). This is achieved through a process called "scrambling" of the technique known to the feedback polynomial binary data stream topology. Because the scrambling polynomial is known, it is possible to recover data by using anti-feedback topology polynomial operating data. PCI Express 8 GT 3.0 in / s effective bit rate per channel of 985 MB / s, in fact, with respect to the channel bandwidth PCI Express 2.0 doubles
November 18, 2010, PCI Special Interest Group officially announced the completion of the PCI Express 3.0 specification to its members in order to build devices based on the new version of PCI Express.
PCIe 3.1
September 2013, PCI Express 3.1 specifications have been announced at the end of 2013 or early 2014 release, the integration of a variety of PCI Express 3.0 specification improvements in three areas: power management, performance and functionality of its release in November 2014.
PCIe 4.0
November 29, 2011, PCI-SIG announced that PCI Express 4.0 provides 16Gb / s bit rate, bandwidth provided by PCI Express 3.0 doubles, while maintaining backward compatibility with software support and second-hand machinery interface. PCI Express 4.0 specification will also bring OCuLink-2, which is a substitute Thunderbolt connector. OCuLink version 2 having up to 16 GT / s (a total of 8GB / s × 4 channels), and the maximum bandwidth of the connector Thunderbolt 3 5GB / s. Also, research active and idle power optimization. The final specification is expected to be released in 2017.
In August 2016, Synopsys at the Intel Developer Forum show run PCIe 4.0 test machine. Their intellectual property has been licensed to several company plans to offer its chips and products at the end of 2016.