1. Arm instruction structure includes 32-bit arm instruction set and 16-bit thumb instruction set.
The arm instruction must satisfy the word boundary alignment.
The thumb instruction satisfies the half-word boundary alignment.
When entering the status bit of thumb register Rm from arm, bit[0] = 1, execute BX Rm instruction jump.
When the status bit bit[0] of the arm register Rm entered from the thumb is 0, the BX Rm instruction jump is executed. When the processor enters exception handling, it starts execution from the exception vector address, and the system automatically enters the arm.
Example: From arm to thumb
LDR R0,=Lable + 1
BX R0
Example: From thumb to arm
LDR R0,=Lable
BX R0
The arm processor supports bytes (8 bits), nibbles (16 bits), and words (32 bits).
Big-endian format: The higher byte is stored in the lower storage byte address.
Little-endian format: The higher byte is stored at the higher storage byte address.
Example: 0x12345678 The starting address is: 0x8000
Big: Small:
0x78 0x8003 0x12
0x56 0x8002 0x34
0x34 0x8001 0x45
0x12 0x8000 0x78
7 modes handled by arm:
CPSR[4:0] mode Purpose:
1000 users User mode
privileged mode: {Exception mode: {1001 FIQ fast interrupt
1002 IRQ normal interrupt
1003 SVC software interrupt
1004 abort processing memory failure, realize virtual memory and memory Protection
1005 undefined, processing undefined commands trapped}
1006 system running privileged operating system tasks}
The arm processor has 37 registers in all, divided into: 31 general registers and 6 status registers.
The FIQ processing program does not need to save and restore the interrupt site, so that the FIQ interrupt processing process is more rapid.
R13 (SP): It is called the stack pointer SP. When the application program initializes each exception mode, it must initialize R13 in this mode to point to the corresponding stack. When
exiting the exception mode, it will be saved in the pointer R13 The register value in the stack is popped.
R14(LR): Used to store the return address of the subroutine. After execution, copy the value of R14 to pc, and the subroutine can return.
R15(PC): Write an address value to R15, and the program will jump to this address.
Status register: CPSR, SPSR
CPSR 1, 4 condition code flags: negative, zero, carry, overflow
2 , 2 interrupt prohibition bits
3, 5 coded bits
4, 1 indicating arm or thumb
NZCV---IFT M4 M3 M2 M1 M0
Condition code flag Reserved bit Control bit
Abnormal Vector Address Table: Abnormal Interrupt Type
Address Type Enter Mode Enter I State Enter F State Priority
0x0000 0000 Reset Management Disable Disable 1
0x0000 0004 Undefined instruction Undefined Disable F 6
0x0000 0008 SWI Management F 7
0x0000 000C Abort Abort F 5
0x0000 0010 Data aborted Abort F 2
0x0000 0014 Reserved Reserved F
0x0000 0018 IRQ interrupt F 4
0x0000 001C FIQ fast interrupt Disable Disable 3
S3C2440 is divided into three parts: arm902T, AHB bus, APB bus.
ARM920t core 16-bit/32-bit RISC microprocessor.
AHB is used to connect high clock frequency and high performance system modules.
APB provides a simpler interface with low performance and slow peripherals.
ADC adder with carry
ADD adder
AND logic and
B branch jump
BIC bit clear
BL with connection branch jump
BX branch and state switching jump
CDP coprocessor data processing
CMN negative number comparison
CMP comparison
EOR logic XOR
LDC Load digital data, from memory to coprocessor, coprocessor loads
LMD to load digital data, from memory to multiple registers, stack operation
Register addressing:
MOV R1, R2; R1 <R2
SUB R0, R1, R2; R0 <R1-R2
Immediate addressing:
ADD R0,R0,#1; R0 <R0 + 1
MOV R0,#0XFF00; R0 <0XFF00
Register shift addressing:
MOV R0, R2, LSL #3; R0 <R2 << 3
ADD R3, R2, R2, LSR #2; R3 <R2 + R1 >> 2
Register indirect addressing:
LDR R0,[R1] ;R0<-[R1]
STR R0,[R1] ;[R1]<-R0
Base address plus offset address
before address change: LDR R0,[R1, #4] ;R0 <-[R1 + 4]
Automatic address change: LDR R0,[R1,#4]! ;R0 <-[R1 + 4],R1 <- R1 + 4
! Automatic indexing function
Post indexing mode: LDR R0,[R1],#4; R0 <- [R1] to transmit data, R1 <- R1 + 4 to transmit address
Example:
LDR R0 ,[R1,R2] ;R0 <- [R1 + R2]
LDR R0,[R1,R2,LSL#2] ;R0 <- [R1 + R2*4]
Data transfer instruction MOV
MOV R1, R2; transfer the value of register R0 to register R1, the same as
MOV PC, R14
MOV R1, R0, LSL #3
Reverse data transmission: MVN
MVN R0, #0; Reverse 0 and transmit to R0
Comparison instruction: CMP
CMP R1, R0; subtract R1 and R0, and set the CPSR flag according to the result
Clear the BIC bit
BIC R0, R0, #0XB; clear the 0, 1, 3 bits in R0, and the rest remain unchanged
B jump
CMP R1, #1; the value of R1 minus 0, set the flag bit
BEQ Lable of CPSR ; jump conditionally, when the flag bit Z of CPSR is set, the program jumps to Lable
Transfer instruction BX with state switching
If the lowest bit in Rn is 1, set the T flag of CPSR to 1 and switch to the Thumb instruction set
MOV R6, #0X8000
BX R6; switch to the Thumb instruction at address 0x8000
The transfer instruction BL
BL Lable with return ; the program jumps to Lable unconditionally for execution, and saves the value of PC in R14 at the same time.
Transfer instruction BLX with return and state return
Multiply instructions and multiply-add instructions (MUL, MLA)
MUL R0, R1, R2; R0 = R1 * R2
MULS R0, R1, R2; R0 = R1 * R2 At the same time set CPSR related flags
MLA R0, R1, R2, R3 ; R0 = R1 * R2 + R3
MLAS R0, R1, R2, R3; R0 = R1 * R2 + R3 at the same time set CPSR related flags
Long multiplication instructions (SMULL, UMULL)
SMULL represents 64-bit signed multiplication operations:
SMULL R0, R1, R2, R3, R4; R0 = the bottom 32 bits of (R2 * R3), R1 = the high 32 bits of (R2 * R3) Bit
UMULL represents 64-bit signed multiplication:
UMULL R0, R1, R2, R3, R4; R0 = the bottom 32 bits of (R2 * R3), R1 = the high 32 bits of (R2 * R3)
Word data load command: LDR, there is an example above.
Byte data load command: LDRB
LDRB R0, [R1]; Read the byte data with the memory address R1 into register R0, and clear the upper 24 bits of
R0 to 0 LDRB R0, [R1,#8]; Read the byte data of the memory address R1 + 8 into the register R0, and clear the upper 24 bits of R0 to 0.
Half-word data load instruction: LDRH
LDRH R0, [R1]; Set the memory address to Read the nibble data of R1 into register R0, and clear the upper 16 bits of
R0 to 0 LDRH R0,[R1,#8]; read the nibble data with the memory address of R1 + 8 into register R0, and set R0 Clear the upper 16 bits of
R0 LDRH R0,[R1,R2]; read the nibble data with the memory address R1 + R2 into register R0, and clear the upper 16 bits of R0 to 0
Word data storage instructions: STR
STR R0,[R1],#8; R1 <- R0 to transfer data, R1 <- R1 + 8 to transfer address
STR R0,[R1,#8]; R1 + 8 <- R0
byte data Storage instruction: STRB transfers the bottom 8-bit byte data in the source register to the memory
STRB R0,[R1]
STRB R0,[R1,#8]
Half-word data storage: STRH transfers the 16-bit byte in the source register Data is transferred to the memory
STRH R0,[R1]
STRH R0,[R1,#8]
Word data exchange instruction: SWP
SWP R0, R1, [R2]; R0 <- R2, R2 <- R1
Byte data exchange instruction: SWPB high 24 bits are cleared, low 8 bits are exchanged
SWPB R0, R1, [R2]; R0 <- R2, R2 <- R1
Data transfer from program status register to general program register: MRS
MRS R0, CPSR; R0 <- CPSR
MRS R0, SPSR; R0 <- SPSR
data transfer from general program register to program status register: MSR
MSR CPSR, R0; CPSR <- R0
MSR SPSR, R0; SPSR <- R0
MSR CPSR_C, R0; CPSR <- R0 only modify the control bit field
ARM microprocessor can support 16 coprocessors,
1, data manipulation instructions: CDP
CDP P2,5, C12, C10, C3, 4; complete the initialization of coprocessor p2, let p2 perform operations on c10, c3 5 And 4, and store the result in c12.
2. Data load instruction: LDC P5, C3, [R0]; P5's C3 <- R0
3, data storage instruction: STC P8, C8, [R2,#4]!; (R2 +4) <- P8's C8 , R2 <- R2 + 4
4, the data transfer instruction from the register to the coprocessor: MCR
MCR P3,3,R0,C4,C5,6; the data in R5 is transferred to the C4 and C5 of P3
5, the coprocessor Data transfer instructions to the register: MRC
MRC P15,2,R5,C0,C2,4; the data of the P15 register is transferred to R5, C0, C2 are the coprocessor registers, which store the original operand, and the opcode 1 is I. Opcode 2 is 4.
Software interrupt: SWI
MOV R0, #34; set the function number to 34
SWI 12; generate software interrupt, the interrupt number is 12
Symbol definition indicator:
GBLA defines global arithmetic variables, initialized to 0
GBLL defines global logic variables, initialized to false
GBLS defines global string variables, initialized to NULL
Example: GBLS S1; declare global string variable S1
local variable declaration:
LCLA
LCLL
LCLS;
Set the variable value as above :
SETA
SETL
SETS; the meaning is the same as above.
Example: S1 SETS "string"
Give the symbol name a constant value:
num2 EQU 25; Assign a value of 25 to the symbol num2
ADR is a small-range address read pseudo-instruction, which reads the address value based on the relative offset of the PC into the register. What ldr obtains is the value of memory, indirect addressing like a pointer.
test1
MOV r1, #0
ADR r2, test1; generate a SUB instruction, load the addresses test1 to r2,
the two main purposes of using LDR, 1 is when the value of an immediate value is out of range, MOV and MVN instructions cannot be used When loading into the register, use LDR instruction to generate a literal pool constant, 2 is to load a relative program or external address into a register.
Commands in assembly language cannot be mixed case.
PC stands for program counter, and the pipeline uses three stages, so instructions are executed in three stages:
1. fetch instruction (load an instruction from memory); 2. decode (identify the instruction to be executed); 3. execute (processing Instruction and write the result back to the register).
And R15 (PC) always points to "fetching" instructions, not to "executing" instructions or "decoding" instructions.
Generally speaking, people habitually agree to take "the instruction being executed as the reference point" and call it the current first instruction, so the PC always points to the third instruction.
When in the ARM state, each instruction is 4 bytes long, so the PC always points to the address of the instruction plus 8 bytes, that is: PC value = current program execution position + 8;
The embedded processor S3C2440 can work at a 400MHZ clock frequency, so a clock management unit is integrated on the chip, which is mainly composed of a phase-locked loop and a frequency divider.
The clock signals inside the S3C2440 chip are FCLK, HCLK, and PCLK.
S3C2440 has two phase locked loops: MPLL and UPLL. MPLL generates three kinds of signals: FCLK, HCLK, PCLK, FCLK is used for arm920T, HCLK is used for AHB bus, PCLK is used for APB bus
, the clock signal generated by USB phase-locked loop UPLL UCLK is used for USB, UPLL is dedicated for USB device
/* Setting MPLLCON(0x4C000004) = (92<<12)|(1<<4)|(1<<0)
* m = MDIV+8 = 92+8=100
* p = PDIV+2 = 1+2 = 3
* s = SDIV = 1
* FCLK = 2*m*Fin/(p*2^s) = 2*100*12/(3*2^1)=400M
System clock initialization
Basic settings after powering on the system:
ldr r0, =0x53000000 //Turn off the watchdog timer
ldr r1, =0
str r1, [r0]
/* Set MPLL, FCLK: HCLK: PCLK = 400m: 100m: 50m */
/ * LOCKTIME(0x4C000000) = 0xFFFFFFFF *///Set to the default value
ldr r0, =0x4C000000
ldr r1, =0xffffffff
str r1, [r0]
/* CLKDIVN(0x4C000014) = 0X5, tFCLK:tHCLK:tPCLK = 1:4: 8 *///Set the three basic ratios
ldr r0, =0x4C000014
ldr r1, =0x5
str r1, [r0]
/* Set the CPU to work in asynchronous mode*/
mrc p15,0,r0,c1,c0,0
orr r0,r0,#0xc0000000 //R1_nF:OR:R1_iA
mcr p15,0,r0,c1,c0,0
/* Set MPLLCON(0x4C000004) = (92<<12)|(1<<4)|(1< <0)
* m = MDIV+8 = 92+8=100
* p = PDIV+2 = 1+2 = 3
* s = SDIV = 1
* FCLK = 2*m*Fin/(p*2^s) = 2*100*12/(3*2^1)=400M
*/
ldr r0, =0x4C000004 //设置fclk为400MHZ
ldr r1, =((92<<12) | (1<<4) | (1<<0))
str r1, [r0]/* Once the PLL is set, the lock time will be locked until the PLL output is stable
* Then the CPU works at the new frequency FCLK
*/
/* Set the memory: sp stack*/
/* The distinction is nor/nand start
* Write 0 to 0 address, and then read it out
* If you get 0, it means that the content at address 0 has been modified, it corresponds to ram, this is nand start
* Otherwise, start with nor
*/
mov r1, #0
ldr r0, [r1]
str r1, [r1]
ldr r2, [r1]
cmp r1, r2
ldr sp,=0x40000000+4096
streq r0,[r1]
bl main
halt :
b halt
Timer clock frequency = PCLK / ((8-bit prescaler + 1) * clock divider value)
The double-buffering feature of TCNTBn and TCMPBn ensures that the timer produces stable output by changing the frequency and duty cycle.
The PWM pulse width is realized by TCMPBn, and the frequency is determined by TCNTBn.
Watchdog timer operating frequency = PCLK / ((prescale value + 1) / division factor)
The storage controller of S3c2440 includes the following features:
1. The system supports large/little endian data storage format
2. The storage space is divided into 8 banks, each bank has 128M bytes of space, and the total addressable space is 1GB. Use nGCS0 ~nGCS7 serves as the corresponding bank selection signal.
3. Except bank0, all other banks can be accessed by programming, with widths of 8, 16, 32 bits.
4. Bank1 ~ bank5 can use ROM and SRAM, bank6 and 7 can use ROM/SRAM/SDRAM
5. Bank0~bank6 start address is fixed, bank7 start address and size are programmable.
The storage system is generally composed of Flash (flash memory) and SDRAM.
Nor flash features: small capacity, high cost, high reliability, short life span, and fast reading speed. The system can run commands directly on norflash to start and boot the system. Mainly used to store startup code.
nandflash: large capacity, low price, long life, fast writing speed, can not be used for main memory, can only read and write per sector, can be used as a small hard disk. Mainly used to store data and programs. You can also start and boot the system from nandflash, and execute the main program on SDRAM.
Generally use bank6 and bank7 as SDRAM storage area in embedded hardware system.
The data bus of bank0 can be configured in 16-bit and 32-bit widths. Bank0 is used as a boot ROM, mapped to 0x00000000. Therefore, the bus width of bank0 is determined in the first ROM access, and the method is through the logic level of OM[1:0] at reset.
When nandflash is started, the nandflash controller will automatically copy the first 4K data to SRAM and map the data on SRAM to nGCS0 (0x000000000). The system boots from SRAM
Norflash startup: OM1 and OM0 pins need to be configured according to the bit width of norflash. When the bit width is 16 bits, OM1 and OM0 should be low and high respectively, and vice versa when the bit width is 32 bits. At this time norflash is mapped to address 0x00000000