FPGA development diary based on Xilinx7 xc7a35t (4)
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Let's proceed to the last lesson before actual combat development: Verilog hardware language learning.
This lesson will start with some basic knowledge and data types, and the next lesson will cover operators and assignment statements.
Verilog HDL language is one of the two most popular hardware languages at present, because the design of this language largely refers to the idea of C language, so students who have learned C language before can easily master this language.
First of all, there are a total of the above four logic states in the Verilog development environment.
There are three ways to represent numbers in Verilog:
1. <
Bit width>'<Base><Number> 2. <Base><Number> (This method lacks a bit width, at least 32 bits at this time)
3. <number> (this method defaults to decimal, and the bit width is 32 bits)
Any language has data types. Verilog's data types are divided into:
net and variable.
1. Wire mesh type
As the name suggests, it is actually the quantity connected by wires ("AND" logic operation) inside the FPGA. For example, I configure the output of a D flip-flop to be Q1, and then I define a wire mesh variable A equal to Q1, so A will always change with the value of Q1.
There are two keywords for wire mesh data. The first one is wire, which means wire. It represents the definition of a quantity, which will always change with the change of another quantity, for example
wire clk_out;
assign clk_out = c_out; // assign here is an assignment statement, we will talk about it later
The meaning of these two lines of code is to define a wire mesh variable clk_out whose value is equal to the c_out variable and changes with the change of c_out.
The second key word is parameter, its function is to define an identifier, which is a constant, similar to the macro definition of the C language. parameter can be redefined.
parameter width = 3;
//The meaning of this line of code is to define a constant equal to 3, which means that when width appears in the next code, the program will automatically replace it with 3.
2. Variables
Variables have only one keyword reg, which corresponds to the register that we can complete the function of the sequential circuit, so reg is also called the register type.
The standard definition of memory is:
reg [msb:lsb] memory [upper:lower]
For example:
reg[3:0] memory1[63:0]
//Define memory1 as an array of 64 4-bit registers
. Commonly used ones are:
reg[4:0] dog; //The number is not specified, the default is one, which is A 5-bit register dog is defined.
That's it for the introduction of data types. Before we talk about operators and assignment statements in the next lesson, we also need to say some precautions in the Verilog language:
- The Verilog program is composed of modules, and each module is nested in the declaration of module and endmodule.
- Each source file can only have one top-level module.
- Each module needs to define a port, such as module A (input b,outout c) //Define a module A, which has an input b and an output c.
- The timing part is in the always block, in which only register variables can be assigned.
- The net variable can only be assigned outside the always block.
- The Verilog program has a free format, multiple sentences can be written on one line, and one sentence can also be written in multiple lines.
- Except for endmodule, begin, end, fork, and join, each statement and data definition must have a semicolon at the end.
- You can use / … / and / /… for comments.
This is the end of this lesson, and soon we will update the next lesson to end the verilog learning and enter the actual combat link. If you want to do practical operations, please download Vivado (version 2017 at least) from the Xlinx website and register to get lisence for free.
Thanks for watching!