Design process
(front-end design; back-end design)
(1)
[1.1] System structure analysis and design
[1.2] RTL coding
[1.3] Functional verification
(2)
[2.1] Logic synthesis
[2.2] PreLayout STA
[2.3] Formal verification [between RTL Code and Logic Synthesis Netlist]
(3 )
[3.1] FloorPlan
[3.2] Placement
[3.3] Insert Clock Tree
[3.4] Global Routing
(4)
[4.1] Formal Verification [between Netlist for Logic Synthesis and Netlist with CT Information]
[4.2] STA
(5)
Detailed Routing DRC
(6)
PostLayout STA
(7)
Tape-out
Partitioning, the chip is divided into functions at the TOP-1 level, divided into IO Pads, boundary scan logic, core function logic, and PLL clock modules
1) When coding at the RTL level, you should try to avoid coding by instantiating standard unit gates.
Harm: Reduce code readability; when using new technology or unit library, you need to modify the code repeatedly
2) Not assigning all conditional branches to cause potential The sensitive list in the Latch and always blocks is incomplete, blocking and non-blocking assignments
3) When defining the timing block, some signals do not need to be reset, and may be reset together to cause different from what we imagined
4) Try to avoid using the clock as a signal Use, no problems will be found during RTL verification, and ignoring the control of clock skew in the back-end design will cause accidents
In order to better synthesize and STA, the design needs to be divided, and the parts that have data exchange between asynchronous clock domains are handled separately, and other modules work in a single synchronous clock domain.
The metastability problem between asynchronous clock domains is eliminated by using two-level flip-flops (single bit data).
In the synchronous clock domain, the metastability problem is the hold problem. Use EDA tools or insert Buffer to eliminate
multiple received control signals. The problem caused by the skew may be caused by the skew or transmission delay of the launch clock.
For multi-bit wide data, use asynchronous FIFO or handshake protocol
Reset strategy
Removal problem, it is necessary to ensure that all flip-flops leave the Reset state within the same beat, and the Reset signal cannot be too close to the clock edge when the Reset signal is completed, to prevent entering the metastable state
[Synchronous reset]
Advantages: The reset time occurs on the edge of the clock, which can prevent the reset signal Glitch.
If the reset signal is generated internally, you must ensure that the Reset pulse is wide enough, at least two cycles, so that the clock can take the
shortcomings: When powering on, some circuits cannot be reset; during synthesis, the logic of synchronous reset may be moved to the D input of the flip-flop, as a normal signal processing, due to the transmission load and delay of the Reset signal, it will cause a longer delay on the DataPath
[ Asynchronous reset]
Advantages: No active clock is required, DataPath is very clean.
If asynchronous reset has Glitch, the chip can enter the reset state, and the reset can be accepted through the two-level DFF, and then the reset trigger can be used through the Tree
Gated clock
Advantages: reduce power consumption, area, simplify logic, increase frequency
Bus implementation:
Method 1: Use a three-state bus.
Advantages: The components hanging on the bus can be distributed in various parts of the chip.
Note: It is necessary to ensure that no bus conflict occurs at any time. In order to eliminate hidden dangers, one hot code can be used; Connect to the pull-up resistor to prevent uncertain bus data generated by not driving the bus for a period of time.
Disadvantages: The capacitive load caused by multiple circuit units/bus layouts connected to the bus will adversely affect performance and area; DFT design brings difficulties
Method 2: Adopt a bus with multiple selection structure
and use it in non-custom ASIC