1 Choose a verilog book with a relatively complete layout and reasonable layout
Verilog, as the most popular FPGA development language now, is of course the foundation of entry. Here I recommend to you two books that have been collected for many years, one is the international standard of verilog2001, and the other is a highly comprehensive handwriting The grammar explanation book, the following is the Baidu network disk link, all free:
Link: https://pan.baidu.com/s/1tstjmKqFcDEkoH1hd43IXA Password: b17x
Please remember: don't read the grammar book before learning FPGA!
It is strongly recommended to use the above two books as a reference book, that is, to directly look up if you do n’t understand. Each review will deepen the impression, remember the common grammar firmly, and do n’t waste time to remember the uncommon grammar.
2 Learn from the simplest code
After finding the reference book, find the simplest basic example (with simulation routines) and start looking at it. After reading, use ISE or Vivado to synthesize, and then look at the RTL diagram, you can see what kind of digital circuit these codes are finally translated into.
Immediately followed by simulation or on-board measurement: using the simulated signal input into the module you write, you can clearly know what the final circuit output is, and whether it is consistent with what you think. If they are inconsistent, find the cause of the inconsistency. For simple designs, there is no difference between the simulation and the actual board.
In addition: understand what circuit the code you write is the core of the entire FPGA design forever! If you find that one day you are very clear about the code you wrote about yourself, then congratulations on getting started! In other words, it is necessary to learn to look at your code with machine thinking. Only by synthesizing can you understand the comprehensive laws of xilinx compilers (which will also be explained in detail in the public account in the future). It is the most important to use machines to understand machines. Good understanding!
Below I share some cases suitable for beginners, in order from easy to difficult:
1.N bit counter (FPGA integrated counter is different from the digital book, please carefully compare)
2.LED control, that is, the control of single signal output law, such as output 1s flash once, etc.
3. Use the state machine to control the LED, such as button A, press it to flash once every 0.5s, press button A again to flash once every 1s, etc., you can freely write your own.
4. Any integer frequency division
5. DDS design
6. Simulate serial communication, such as 9600 baud rate, 1 bit each for start bit and stop bit, no parity bit. Just communicate with the host computer in this way to see if it works properly. If you can realize that you have made a qualitative leap, you can basically understand how verilog designs the circuit.
7. SPI communication is also a relatively simple protocol, you can try it regardless of master or slave
8. I2C communication, the difficulty is almost the same as SPI
9. Learn to use common IP cores
Here, the editor also attaches some of the code when I studied, and the ISE video tutorial. The following is a link to the Baidu network disk:
Super multi-instance source link: https://pan.baidu.com/s/1tt1W9dlFMI_CqlXd_ksa6A Password: zkmq
ISE video tutorial link: https://pan.baidu.com/s/1KfhLXPAYaLq5IFSxemFxvg password: g97e
3 Advanced tutorial
In general, advanced should master the following points:
1. Reasons and methods of timing constraints, can be proficient in applying the most basic clock cycle constraints, timing exception constraints, asynchronous clock domain constraints, synchronous reset constraints, high fan-out constraints
2. Clear the distribution of clock resources inside the xilinx chip, and can know whether its own code and constraints can let the compiler use more optimized routing layout.
3. Clear distribution and reasonable use of internal embedded hard core
4. Understand the common methods of correct transmission of common asynchronous clock domain: handshake signal, asynchronous FIFO, synchronizer
5. Can understand some basic parameters in the timing report
4 Advanced tutorial
Advanced tutorials are endless, but if you learn the following points you have stepped into the ranks of experts:
1. All common timing constraints and timing exception constraints of FPGA, including logic locking methods, can be used correctly
2. Able to make a reasonable plan to improve the timing according to the timing report
3. Know the approximate limits of various timing optimization schemes
5. Able to implement some complex algorithms on FPGA platform: such as PID adjustment, FFT change, FIR filter, neural network, etc.
6. For large-scale, large-throughput logic design, you can have a rough overall plan when you need to input. You should be able to think about how to do the clock plan, reset plan, high-speed interface plan, or whether you can do it.
In short, the high-level tutorial will make people farther away from the FPGA, using FPGA as the underlying platform to implement some abstract and advanced theories. In fact, whether it is CPU or FPGA are tools, the algorithm implementation in the tool is the most important.
