"Introduction to Operating System" study notes (3): CPU virtualization (mechanism)

$CPU virtualization includes both micro and macro aspects. The micro level is the mechanism for implementing process switching, and the macro level is the \\ policy of process scheduling.$

Processes issue interrupt instructions through system calls to submit CPU control, so interrupt (interrupt) is the main mechanism to achieve process switching, and it is also the "engine" that drives the operating system. But before formally introducing the interruption mechanism, it is necessary to introduce the reasons for the interruption mechanism and the applicable environment.

CPU dual mode (Dual-mode)

The instructions of the process are directly run on the CPU, but the process of the process inevitably requests the system resources such as I / O from the operating system, and sometimes the operating system needs to switch processes. These all need to operate in the kernel space. How can the operating system kernel meet the needs of the process while avoiding the dangerous operations of the process (such as unauthorized modification of the operating system kernel)?

First of all, we can separately divide an area in the address space to store key content such as system kernel code data and process control blocks. The remaining area is used for running user programs, which are called kernel space and user space , respectively . Then assign different levels to the instructions running in kernel space and user space. The instruction level in kernel space is high, called privileged instructions , which can access all memory and registers, and the instruction level in user space is low, called non-privileged instructions . Finally, according to the instruction level of the CPU operation, distinguish the CPU operation mode. When the CPU runs privileged instructions, the CPU is in kernel mode , otherwise it is in user mode .

Intel's x86 processors are accessed through the Ring level. There are 4 levels from Ring0 to Ring3. The R0 layer has the highest authority, and the R3 layer has the lowest authority. Intel's original idea was that applications work on the R3 layer and can only access data on the R3 layer; the operating system works on the R0 layer and can access data on all layers; while other drivers are on the R1 and R2 layers. In fact, Linux and Windows operating systems only select the R0 layer and R3 layer to run operating system instructions and application program instructions- dual-mode (dual-mode) .

1.内核模式(kernel mode)：操作系统运行程序，可以使用特权指令，访问所有内存和寄存器。
2.用户模式(user mode)：应用程序运行程序，只能使用一般指令，访问特定的内存和寄存器。

The CPU mode of the x86 system is mainly determined by the current program privilege level CPL and the program status word PSW . CPL stands for the currently executed code privilege level and is stored in the 0th and 1st bits of CS (code register) and SS (segment register). The 12th and 13th bits of the program status word PSW IOPL are the input and output privileged bits (two (Bits represent four levels from 0 to 3). When CPL> IOPL, you can execute privileged instructions like IN and OUT, which is equivalent to the CPU in kernel mode. Conceptually, we can simply understand that there is a mode bit register in the CPU . When the mode bit is 0, the CPU is in user mode, when the mode bit is 1, the CPU is in kernel mode, and the modification of the mode bit Determined by interruption.

Safe control transfer

Process switching The process of returning CPU control to the operating system requires switching from user mode to kernel mode, and the operating system allocates CPU to the process and needs to switch from kernel mode to user mode. Therefore, after distinguishing the meaning of user mode and kernel mode, we also need to understand how to safely implement mode switching and controller transfer.

Trigger event

At present, there are two main events to trigger the switch from user mode to kernel mode: exception and interrupt.

Exception : The exception is generated by the currently executing user process. Exceptions include arithmetic overflow, division by zero, out of bounds when accessing addresses, attempting to use privileged instructions or executing "traps", etc. At this time, the hardware suspends the current running process, switches the CPU operating mode, and goes to exception handling Program (exception handler) or error handler (debugger).

Interrupt (interrupt) : An interrupt is an internal signal that an external event occurs and communicates to the process. It is generated to support parallel operations between the CPU and the device. An event occurs outside the CPU. An int interrupt instruction is generated after the event occurs, causing the CPU to suspend the ongoing process and retain the scene (context), go to the interrupt handler (interrupt handler), and issue an iret interrupt return instruction to return to the breakpoint after processing , Continue to execute the interrupted process. In addition, interrupts between processes are another common interrupt .

The sources of exceptions and interrupts are different, and the occurrence process is similar. Therefore, they are discussed for convenience.

2. Interrupt handling

The interrupt / exception mechanism is one of the core mechanisms of the operating system, and requires hardware and software to cooperate with each other. The hardware captures the interrupt / exception request from the interrupt source through the interrupt implicit instruction, responds to the interrupt and transfers CPU control to the interrupt / exception handler, and the handler needs to identify the type of interrupt / exception and handle it accordingly.

Interrupt capture

hardware saves the scene While
querying the interrupt vector table, the CPU needs to prepare for the software to handle the interrupt. First of all, the CPU needs to save the program status word PSW and program counter PC of the original process on the system kernel stack so that the interrupt process can be accurately returned to the original process interruption point after the interrupt processing. Second, the CPU modifies the mode bit register according to the interrupt instruction and switches the CPU to kernel mode.

程序计数器（Program Counter）是用于存放下一条指令所在单元的地址的地方。
程序状态字（Program Status Word, PSW）又称状态寄存器，主要用于反映处理器的状态及某些计算结果以及控制指令的执行。用一个专门的寄存器来指示处理器状态。

Query interrupt vector table

中断向量：一个内存单元，存放中断处理程序入口地址PC和程序运行所需的程序状态字PSW。

The CPU queries the interrupt vector table according to the interrupt code, obtains the entry address of the corresponding interrupt handler, and sets the PC to this address. A new instruction cycle begins, and the CPU control is transferred to the interrupt handler.

Handling interrupts

中断处理程序(interrupt handler)：响应一个特定中断后，操作系统会执行的特定函数。Linux系统的中断处理程序是按照特定类型声明的C函数。

First, the interrupt handler saves the remaining register information of the original process to the kernel stack; then analyzes the cause of the interrupt / exception and executes the corresponding function. For example, the interruption caused by the process switching, the new process to be executed is selected according to the process scheduling strategy, and the PC is set as the address of the new process. Finally, after the interrupt is executed, an interrupt return instruction is issued, and the CPU detects the instruction, and then runs the original process or the new process.

Switching between processes

There are two main methods for process switching: one is to wait for the ongoing process to use the system call to issue an interrupt cooperation method, and the second is to set a timer to force a non-cooperative method of interruption. The following two methods are used as examples to summarize the process of interrupt processing.

1. Cooperative Approach: Waiting for System Calls (A Cooperative Approach: Wait For System Calls)

Operating system startup At
startup, the CPU is in kernel mode to run the operating system. The system initializes the trap vector table (trap table) and informs the hardware of the address of the interrupt handler in the table.

Execute system call

1. The system call is the only interface provided by the operating system to the user process. This method will set a displayed system call at the end of each process, and the function of the system call will issue an interrupt instruction;
2. The hardware captures the interrupt instruction, saves the register content to the kernel stack, modifies the mode bit to make the CPU switch to kernel mode, and leads the interrupt handler according to the interrupt code look-up table;
3. The interrupt handler uses the process scheduling strategy to select the process to run, and executes the interrupt return instruction return-from-trapto return to user mode after execution .
   

In addition, when the process does something illegal, it will generate an abnormal instruction to forcefully deprive the process of CPU control.

But if the running process contains an endless loop, then the collaboration method will fail, and the operating system needs to obtain CPU control.

2. Non-Cooperative Approach: The OS Takes Control

The non-cooperative method is to deploy a timer to count the running time of the current process. When the running time exceeds a certain limit (eg Xms), the timer will actively issue an interrupt instruction to forcefully stop the running of the current process and hand over CPU control to the operating system. .

References

"Operating System: three easy pieces"
"Operating Systems: Principles and Practice"
"Operating System Concepts"
operating system principles Peking University Chen Xiangqun