illustrate
Record a written test by Fa Ge on the evening of April 19th. Share it with IC people who need it.
Position: Digital IC Design Verification (Hefei, Anhui)
Reprinting requires my consent!
My opinions are not necessarily accurate, welcome to exchange and correct in the comment area~~
1. (20 points) For a very classic computer science question, please see:
This number and electricity topic can only be said to be very classic; the most important thing is to deal with constraints.
Then, regarding the simplification of constrained items, here is my opinion for reference.
The general form of the constraint item is: and or formula = 0 (if it is not in this form, it is best to change to this form) ; such as BC = 0; or AB + CD = 0; ABC + CD = 0; etc. .
The idea of direct solution is to draw a Karnaugh map, and draw X on the Karnaugh map grid corresponding to each item on the left side of the constraint equal sign , that is, an irrelevant item. For this question, it is to draw X on the grid corresponding to BC ( that is, B=1, and C=1 ).
The specific solution is given below:
2. (5 points) Short answer question, what is the function of synthesis tools in ASIC flow? When synthesizing, the SDC file is required for constraints. Please list the syntax of 3 SDCs.
To give my opinion: The role of synthesis is to map the HDL code to the gate-level netlist in the device library.
SDC syntax enumeration:
set_input_delay delay_value -clock clock_ref [–max] [–min] [–clock_fall] [-rise] [-fall] [-add_delay] input_list
create_clock[-add] [-name <clock_name>] -period [-waveform<edge_list>]
set_false_path -from [get_clocks CLKA]-to [get_clocks CLKB]]
3. (10 points) Intellectual questions (reasoning questions)
The text is too annoying, so I just gave up. Show everyone:
(1) 2 12 1112 3112 132112, what is the next number? give reason;
The next number is 311322
(2) A thief managed to get into the bank's vault. In the vault he found a hundred chests, each full of gold coins. However, only one box contained real gold coins, and the remaining 99 boxes contained fake gold coins. The shape and texture of real and fake gold coins are exactly the same, and no one can tell them apart with the naked eye. They have only one difference: the real gold coins weigh 101 grams each, while the fake gold coins weigh 100 grams. In the vault is an electronic scale that can accurately measure the weight of any item down to the gram. But unfortunately, this electronic scale is connected to the bank's alarm system, and it will be invalid as long as it is used once. Excuse me, how can a thief find the box containing real gold coins by using the electronic scale only once?
This topic is very classic:
4. (10 points) Choose any project you have participated in, briefly describe the project content and process, describe the tasks you undertake in the project, pick a problem you think is difficult, and explain the solution.
5. (5 points) Write a bubble sort function and test program in python.
def bubbleSort(arr):
n = len(arr)
# 遍历所有数组元素
for i in range(n):
# Last i elements are already in place
for j in range(0, n-i-1):
if arr[j] > arr[j+1] :
arr[j], arr[j+1] = arr[j+1], arr[j]
arr = [64, 34, 25, 12, 22, 11, 90]
bubbleSort(arr)
print ("排序后的数组:")
for i in range(len(arr)):
print ("%d" %arr[i]),6. (15 points) Write a Round Robin arbiter in Verilog. The module ports are as follows:
input clock;
input reset_b;
input [N-1:0] request;
input [N-1] lock;
output [N-1] grant; //one-hot
The lock input signal here indicates that the requester has received the arbitration permission, and the arbitrator cannot start a new arbitration before the corresponding lock is pulled low. (It can be simply understood as arbiter occupation)
This question requires parameterized programming, and the parameters can be adjusted when the module is instantiated. That is to say, you cannot write a fixed parameter, such as a module with N=8.
Reference waveform diagram:
Ideas for this question reference:
Verilog Implementation of Round-Robin Algorithm
Combined with the needs of the topic, I will give my opinion here:
Design source code:
// =================================================================================== // 功能： // -1- Round Robin 仲裁器 // -2- 仲裁请求个数N可变 // -3- 加入lock机制（类似握手） // -4- 复位时的最高优先级定为 0 ，次优先级：1 -> 2 …… -> N-2 -> N-1 // By：Xu Y. B. // =================================================================================== `timescale 1ns / 1ps module Round_Robin_Arbiter #( parameter N = 4 //仲裁请求个数 )( input clock, input reset_b, input [N-1:0] request, input [N-1:0] lock, output reg [N-1:0] grant//one-hot ); // 模块内部参数 localparam LP_ST_IDLE = 3'b001;// 复位进入空闲状态，接收并处理系统的初次仲裁请求 localparam LP_ST_WAIT_REQ_GRANT = 3'b010;// 等待后续仲裁请求到来,并进行仲裁 localparam LP_ST_WAIT_LOCK = 3'b100;// 等待LOCK拉低 // 模块内部信号 reg [2:0] R_STATUS; reg [N-1:0] R_MASK; wire [N-1:0] W_REQ_MASKED; assign W_REQ_MASKED = request & R_MASK; always @ (posedge clock) begin if(~reset_b) begin R_STATUS <= LP_ST_IDLE; R_MASK <= 0; grant <= 0; end else begin case(R_STATUS) LP_ST_IDLE: begin if(|request) //首次仲裁请求 begin R_STATUS <= LP_ST_WAIT_LOCK; grant <= request & ((~request)+1); R_MASK <= ~((request & ((~request)+1))-1 | (request & ((~request)+1))); end else begin R_STATUS <= LP_ST_IDLE; end end LP_ST_WAIT_REQ_GRANT://处理后续的仲裁请求 begin if(|request) begin R_STATUS <= LP_ST_WAIT_LOCK; if(|(request & R_MASK))//不全为零 begin grant <= W_REQ_MASKED & ((~W_REQ_MASKED)+1); R_MASK <= ~((W_REQ_MASKED & ((~W_REQ_MASKED)+1))-1 | (W_REQ_MASKED & ((~W_REQ_MASKED)+1))); end else begin grant <= request & ((~request)+1); R_MASK <= ~((request & ((~request)+1))-1 | (request & ((~request)+1))); end end else begin R_STATUS <= LP_ST_WAIT_REQ_GRANT; grant <= 0; R_MASK <= 0; end end LP_ST_WAIT_LOCK: begin if(|(lock & grant)) //未释放仲裁器 begin R_STATUS <= LP_ST_WAIT_LOCK; end else if(|request) //释放的同时存在仲裁请求 begin R_STATUS <= LP_ST_WAIT_LOCK; if(|(request & R_MASK))//不全为零 begin grant <= W_REQ_MASKED & ((~W_REQ_MASKED)+1); R_MASK <= ~((W_REQ_MASKED & ((~W_REQ_MASKED)+1))-1 | (W_REQ_MASKED & ((~W_REQ_MASKED)+1))); end else begin grant <= request & ((~request)+1); R_MASK <= ~((request & ((~request)+1))-1 | (request & ((~request)+1))); end end else begin R_STATUS <= LP_ST_WAIT_REQ_GRANT; grant <= 0; R_MASK <= 0; end end default: begin R_STATUS <= LP_ST_IDLE; R_MASK <= 0; grant <= 0; end endcase end end endmoduleSimulation file:
// ===================================================================== // 功能：测试模块 Round_Robin_Arbiter 功能 // By：Xu Y. B. // ===================================================================== `timescale 1ns / 1ps module TB_Round_Robin_Arbiter(); parameter N = 4; //仲裁请求个数 reg clock; reg reset_b; reg [N-1:0] request; reg [N-1:0] lock; wire [N-1:0] grant;//one-hot initial clock = 0; always #10 clock = ~clock; initial begin reset_b <= 1'b0; request <= 0; lock <= 0; #20; reset_b <= 1'b1; @(posedge clock) request <= 2; lock <= 2; @(posedge clock) request <= 0; @(posedge clock) request <= 5; lock <= 7; @(posedge clock) lock <= 5; @(posedge clock) request <= 1; @(posedge clock) lock <= 1; @(posedge clock) request <= 0; @(posedge clock) lock <= 0; #100; $finish; end Round_Robin_Arbiter #( .N(N) ) inst_Round_Robin_Arbiter ( .clock (clock), .reset_b (reset_b), .request (request), .lock (lock), .grant (grant) ); endmoduleSimulation results:
Compared with the given reference waveform, the two are consistent.
7. (15 points) About DMA register configuration, DMA register (address 0x81050010) table:
Type indicates the type of reading and writing. Reset means reset value.
Write a C function void dma_driver(void), complete the following requirements step by step:
- Source address (0x30) required to allocate DMA
- Allocate the destination address required by DMA (0x300)
- Set to transmit 128 Byte data
- start DMA transfer
- Wait for the DMA transfer to end
The way the code is written is not unique, here is my opinion: (updated on April 23, thanks to chongwusc in the comment area for pointing out the problem)
void dma_driver(void) { unsigned int *ptr = (unsigned int *)0x81050010; int DMA_SRC_ADDR = 0x30; int DMA_DST_ADDR = 0x300; int DMA_LENGTH = 128; int DMA_START = 0X01; int REG_CLEAR = 0x0; // 根据评论区用户 chongwusc 提出的问题，增加寄存器清零的操作，方便后续通过按位或运算配置寄存器 // 时无BUG *ptr &= REG_CLEAR; // STEP1 *ptr |= DMA_SRC_ADDR << 2; // STEP2 *ptr |= DMA_DST_ADDR << 13; // STEP3 *ptr |= DMA_LENGTH << 24; // STEP4 *ptr |= DMA_START; // 等待 stop while((*prt) & DMA_START) { } }
8. (20 points) The second-order bandpass filter is built with RC components. The passband range is 1kHz~30kHz. The two resistors R are both 10kΩ. What is the capacitance of the two capacitors?
First of all, you have to know what the circuit of the second-order bandpass (RC) filter looks like:
The basic idea is to calculate the transfer function, and then find the cut-off frequency; since R1=R1=10kΩ, the formula is always denoted by R: (If you find any problems with the derivation steps, please leave a message in the comment area in time, thank you )
According to the finally derived expression, for jwRC2, this item, when w tends to infinity, uo/ui tends to zero. Then the critical point of high frequency is wRC2 = 1+2C2/C1 ; (ignore the low frequency item 1/jwRC1 at this time);
Similarly, for the low frequency item 1/jwRC1, w tends to infinite hours, uo/ui tends to zero, then the critical point of low frequency is 1/wRC1 = 1+2C2/C1;
tidy:
The solution process uses MATLAB:
Ideas refer to: RC frequency filter circuit design
So far, Fa Ge’s written test questions on the evening of the 19th have all been sorted out. If you have any questions, please let me know in time (leave a message in the comment area~~)
Come on IC!
suck luck
This is a later story. After a long wait, I finally got the follow-up news today (May 9th) and passed the written examination:
Give encouragement to colleagues who are going to take the written test, come on!