ref measurement and control circuit fifth edition
DA converter
- Main Specifications
- Resolution: The least significant bit of LSB, corresponding to the change of the output analog quantity when a change occurs. In practice, the number of digits of the input digital quantity is commonly used to indicate the resolution (10-bit binary DA converter, resolution 2 − 10 2^{- 10}2− 10 )
- Accuracy:
- Build time
Conversion characteristics
Structure & Principle
Weighted Resistor Network Circuit
I o = − 2 U R R 1 R ∑ i = 1 n d i × 2 − i I_o=-\frac{2U_RR_1}{R}\sum_{i=1}^nd_i\times 2^{-i} Ithe=−R2 URR1i=1∑ndi×2−i
T-shaped R-2R resistor network circuit
U o = − U R R 1 R ∑ i = 1 n d i × 2 − i U_o=-\frac{U_RR_1}{R}\sum_{i=1}^nd_i\times 2^{-i} INthe=−RINRR1i=1∑ndi×2−i
AD converter
principle
Dual Integral AD Converter
- Before conversion, the logic control circuit clears the counter to 0, and the integrating capacitor CCC discharge -> 0
- Start switch: U i U_iINiHereafter U i RC \frac{U_i}{RC}RCINirate at a fixed time T 1 T_1T1Charge the capacitor to make the integrator output voltage UC U_CINCIncrement from 0, start the counter to count the clock pulses from 0
- Arrived at scheduled T 1 T_1T1, count value N 1 N_1N1, the sampling ends, the counter resets to 0, U i U_iINiPolarity, the reference voltage to which the electronic switch will reverse its polarity ± UR \pm U_R± URIt is added to the input of the inverting integrator, the integrator integrates its inverting phase, and the counter recounts and enters the comparison stage
- U C U_C INCWhen it falls to 0, the output terminal of the comparator sends a close signal, the count is closed, and the conversion is over.
- N 2 = N 1 U R U i a v N_2=\frac{N_1}{U_R}U_{iav} N2=INRN1INi v
Successive approximation AD converter
- 6-bit AD converter:
- When the pulse arrives: the register is cleared to 0, the conversion is started, the clock circuit makes the MSB of the successive approximation register MSB=1 (100000), and the DA converter -> U s U_sINs, input U i U_iINiCompare:
- U s < U i U_s<U_i INs<INi: The number is not big enough to keep MSB=1
- The second highest bit = 1, and then converted by DA and U i U_iINiCompare…
- Bit-by-bit comparison until the voltage difference < maximum quantization error, the register is reserved i.e. U i U_iINi, the conversion is complete
- When the pulse arrives: the register is cleared to 0, the conversion is started, the clock circuit makes the MSB of the successive approximation register MSB=1 (100000), and the DA converter -> U s U_sINs, input U i U_iINiCompare:
- nnn operations can completenn -bit AD conversion, high speed, high precision, simple structure