（三）补码转换和译码器

补码转换

`timescale 1ns/10ps

module device(a,a_comp);
input [7:0]a; //括号要写在前面
output[7:0]a_comp;
wire[6:0] b;//按位取反的幅度位
wire[7:0] y;//负数的补码
assign b=~a[6:0];
assign y[6:0]=b+1;//按位取反再加1
assign y[7]=a[7];//符号位不变
assign a_comp=a[7]?y:a;//二选一
endmodule



module device_tb;
reg[7:0] a_in;
wire[7:0] y_out;
device device(.a(a_in),.a_comp(y_out));
initial begin 
	a_in<=0;
	#3000 $stop;
end
always#10 a_in<=a_in+1;

endmodule

数码管

`timescale 1ns/10ps

module device(num,y);
input[3:0] num ;//输入
output[7:0] y;
	reg[7:0] y; //always 语句块里面赋值的变量需要是reg型
	always@(num)//三个为敏感变量，组合逻辑输入
	begin 
		case(num)
		4'd0: begin y<= 8'b00000000; end
		4'd1: begin y<= 8'b00000001; end
		4'd2: begin y<= 8'b00010001;end
		4'd3: begin y<= 8'b00100001;end
		4'd4: begin y<= 8'b10000001;end
		4'd5: begin y<= 8'b00001001;end
		4'd6: begin y<= 8'b00000101;end
		4'd7: begin y<= 8'b00000011;end
		4'd8: begin y<= 8'b00000111;end
		4'd9: begin y<= 8'b00111001;end
		default:begin y<= 8'b00111001;end
		endcase
	end 
endmodule