Cortex-M documentation and CMSIS_5 download address: Overview (arm-software.github.io)
Kernel architecture: Kernel architecture—Xinwen (soc.xin)
core_cm0plus.h
core_cm7.h
cmsis_gcc.h
Cortex-m0 has no interrupt vector register ICER, and m0-plus/m7 has interrupt vector register ICER.
After using __disable_irq(); to turn off the total interrupt, you need __enable_irq to turn on the total interrupt to enable the peripheral interrupt NVIC_EnableIRQ.
| Turn off total interrupts | __disable_irq | #include "cmsis_gcc.h" __ASM volatile ("cpsid i" : : : "memory"); |
| Turn on total interrupt | __enable_irq | #include "cmsis_gcc.h" __ASM volatile ("cpsie i" : : : "memory"); |
| Turn off module interrupts | NVIC_DisableIRQ | core_cm7.h/core_cm0plus.h |
| Turn on module interrupts | NVIC_EnableIRQ | core_cm7.h/core_cm0plus.h |
| Set SP pointer | __set_MSP(start) | #include "cmsis_gcc.h" __asm volatile ("MSR msp, %0" : : "r" (start) : ); |
| Get jump address | void (*user_app)(void) = *(u32 *)(start+4); | Get the entry address of the jump program |
| Jump | user_app(); |
Before jumping, you need to perform the following steps:
1. Turn off peripheral interrupts;
2. Set the SP pointer and reset the pointer;
3. Obtain the entry address of the jump program;
4. Jump.
Examples are as follows:
