1. The origin of consistency
The physical layer conformance test originated from the USB2.0 standard and was promoted and popularized by the USB-IF Association and the industry giant Intel Corporation. Due to the sudden increase in the number of hosts (Host), devices (Device) and hubs (Hub) that adopt the USB2.0 standard , it is necessary to solve the problems of each device
Due to the compatibility and differences between the physical layer and the protocol layer, a unified standardized measurement method was developed to evaluate the signal quality of each device. Conformance testing is similar to black-box testing, and usually only focuses on the signal quality at the external interface of the device. After passing the conformity test approved by the association, the corresponding Logo can be marked. Today, conformance testing has been widely adopted by major standards and protocol organizations, such as HDMI, DisplayPort, USB3.x, SATA/SAS, PCIExpress, ThunderBolt, etc.
Correspondingly, IEEE, another major organization in the industry, also introduced the concept of conformance test in the test of 10/100/1000 BaseT to evaluate the signal quality of each device. In fact, USB2.0 and Ethernet are two of the most successful and enduring interface and communication standards no matter how the times change. Even in the latest 200G/400G standards published by IEEE in recent years, similar test methods are defined.
2. What is conformance testing
A general term for tests that use the same ruler to measure whether the signal quality of a product meets the standards, which is widely accepted in the industry. It is based on the CTS (Compliance Test Specification) defined by various standards and associations. Through the conformance test of the product, in addition to knowing whether the product conforms to the standard test specification, it is also possible to quantify the margin of each index of the signal from the CTS. If the margin is sufficient, it means that the product can be designed for cost reduction, otherwise it needs to be redesigned. For system manufacturers, in the face of rapidly changing markets and fierce competition, reducing product costs is a magic weapon for survival. For upstream chip manufacturers, if the system based on their chips can show a very high margin after conformance testing, it can indicate the performance of their products and provide full confidence and margin for the product design and development of their downstream customers. Quantity for cost reduction design. Therefore, the importance of conformance testing to the entire industry is self-evident.
In recent years, with the development of digital technology and chip integration technology, the proportion of electronic circuit debugging (Debug) in the development of electronic products has become smaller and smaller, and the consistency test has become increasingly important as a link before the final product shipment. The most important use of an oscilloscope.
3. Meaning or elements of conformance testing
- Uniform standard test signal
This unified standard test signal, the English name is Compliance Pattern. Starting from USB2.0, Intel has developed a software package tool (USBHSETTool) specifically for PC systems to send various signals, such as Test Packet for testing eye diagrams. Today, the device under test that supports the USB3.x standard sends an IN packet after power-on. If no ACK packet is detected, it enters the Compliance test mode and sends out various Compliance Patterns. The principle of the PCIExpress standard is similar. There are also special cases, such as the display technology HDMI is not the same, the sink device generally does not have high-speed signal back to the source end, so it is necessary to use an external EDID Emulator to deceive the source end device has an external sink device of a certain format, and the source end device will start output signal. However, the DisplayPort standard and the SATA standard usually need to modify the register configuration test pattern. Some standards also support automatic configuration of test patterns through software for external controllers to cooperate with conformance testing, such as the DP test controller developed by Unigraf and the Thunderbolt controller developed by Wilder.
Why define a unified test signal? Because different code patterns are used for testing, the measurement results obtained are also different. For example, if the 0101 code pattern is used and the 00110011 code pattern is used, the obtained ISI jitter must be different. So in order to unify and standardize the measurement, associations and standard organizations have defined standard test patterns. The most typical one at present is that the USB3.1 standard defines a variety of code patterns for different test items:
Table 1. USB3.x Test Pattern Table
The code pattern CP13-CP16 marked in yellow above is a new code pattern added in the USB3.1 specification for testing the pre/de-emphasis or equalization of the sending end:
Figure 1. Description of USB3.1 CP13-CP16 code pattern
2. Standard connection method, usually a combination of clamps and cables
In addition, in order to unify the test environment, associations and standard organizations also define standard connection methods, usually using standard fixtures and cables developed by associations or third-party companies. Fixtures and cables are usually introduced for the convenience of test connections, which will inevitably introduce test errors and reduce the test margin of the system. Therefore, in the process of conformance testing, it is necessary to require the use of the same testing tool to standardize the measurement and avoid testing differences. Among the current mainstream standards, except for the USB3.x and PCIE fixtures which are still mainly provided by the Intel-led USB-IF and PCI-Sig associations, other standard fixtures can be provided by Wilder. In terms of test connection, the HDMI standard initially needs to connect 3 pairs of Data and 1 pair of CLK for testing at the same time, so the fixture is used to connect the SMA probe and then connect to the oscilloscope for testing, so as to complete the testing of all differential items at one time.
In the definition of standards and specifications, several test points are generally defined. For example, TP1, TP2, TP3, and TP4 are defined in the USB2.0 specification. TP2 is a typical Host test point position, and TP3 is a typical Device device test point. Location. The test points defined by different standards have different meanings. For example, the USB3.x standard mainly defines TP1—the remote test point of the transmitter test, and TP0 usually refers to the near-end test point of the transmitter. It is only used as Informative in the test software of the oscilloscope. test:
Figure 2. Topology illustration of USB3.x test method
In the past two years, after the signal rate has continued to increase to more than 5Gbps, the TPxEQ test point is usually introduced on the test point. For example, in the DP1.4 standard, the defined test point is TP3_EQ. This test point usually represents the signal in the receiving system. The test points after the equalization algorithm are usually undetectable in the actual test. It is necessary to simulate the equalization algorithm of the receiving end in the conformance test software on the oscilloscope:
Figure 3. DP1.4 Test Point Definition and Topology Diagram
3. Standard test algorithm and process
After the device under test sends a standard test pattern and connects to the oscilloscope through the fixture and cable, the oscilloscope acts as the receiving end, and the signal processing method of the analog chip receiving end tests and analyzes the signal. In addition to the conventional electrical characteristic parameter measurement for the signal, Eye diagram and jitter analysis are usually performed as well. The standard test algorithms mentioned in this article mainly refer to clock recovery and eye diagram and jitter analysis methods in the early years, which are relatively simple. In recent years, technologies such as embedding and equalization have been widely introduced into high-speed serial bus systems, and the level of signal analysis algorithms has been greatly improved.
Typical external interface standards such as USB3.x/HDMI2.x/DP1.4 need to test the far-end eye diagram. In the actual connection, the near-end of the device under test, that is, the sending end, is used to pick up the signal with a fixture and then embed the standard provided The cable parameter model simulates the real transmission cable. This lossy cable parameter model brings great attenuation to the signal, and the equalization algorithm (CTLE/FFE+DFE) must be used to restore the signal at the receiving end. The conformance testing software running on the oscilloscope will be fully embedded in the standard equalization algorithm at the receiving end to restore the signal and then perform parameter analysis, eye diagram and jitter testing. Take the DP1.4 standard as an example:
Figure 4 DP1.4 Test Principle Block Diagram
It can be seen that in today's high-speed signal testing, the status and role of conformance testing software are increasingly important. In addition to performing standard test algorithms for analysis and giving test results, the conformance test software can sometimes change some configurations for debugging tests, that is, modify some test configuration parameters and options, which is called DebugMode.
After the test is completed, the conformance test software will organize and output all the test results into a report, and the margin level of each test item will be specially marked in the report, such as the KeThunderbolt N6470B test report shown in the table below, which is divided into three columns in the green box Display measured value, margin and Pass/Fail judgment:
Table 2 Thunderbolt Compliance Test Software Results Report
In fact, many interface standards in the Server, PC and notebook industries today, such as PCIE, SATA, USB3. In the Sigtest software, some different test script files will be defined for different standards and different test points (in the Template folder of the Sigtest installation folder). Standard conformance testing software can also usually call the DLL (Dynamic Link Library) file in the Sigtest program to execute the standard algorithm test of leading companies in this industry.
4. Factors Affecting Conformance Test Accuracy
Earlier we described the meaning and essence of conformance testing. What exactly is conformance testing after? In the final analysis is the margin (Margin). Its essence or ultimate motivation is to reduce costs. For system manufacturers, after the product design is completed, if the conformance test finds that the signal quality has a large margin from the requirements stipulated in the CTS specification, it means that the product can be designed to reduce costs, such as reducing capacitance, Or use cheaper connectors or even reduce the number of PCB layers, etc., all seemingly small cost reduction considerations will be magnified in large-scale mass production, thereby bringing considerable economic benefits. Of course, cost reduction design is not without bottom line, the bottom line is CTS, so many manufacturers in the industry sometimes repeatedly design and test products to find the final balance point, and oscilloscopes play an important role in this process. For the upstream manufacturers of the chip or industrial chain, after the product design is completed, it is also necessary to carry out reference design and do consistency test verification to submit reports to downstream manufacturers to prove the high quality and large margin of their products and give their customers enough Confidence to design for cost reduction.
The test and measurement process will inevitably bring errors, so how to minimize the error or get the highest Margin? In addition to the 3 points we discussed earlier, in addition to ensuring correct conformance testing, it is necessary to consider the equipment. The first is to choose the
When using an oscilloscope, some indicators of the oscilloscope, such as bandwidth, sampling rate, noise floor and jitter, will affect the margin of the compliance test. Bandwidth is an indicator that many people are familiar with. It is often mentioned that the choice of sine wave 3-5 is bandwidth and square wave 9 times frequency.
For general high-speed serial bus data (NRZ encoding), a speed algorithm was mainly used in the past: signal frequency/2*5, such as 5GBps NRZ signal, the fundamental frequency is 2.5GHz, using 2.5GHz*5 =12.5GHz or above is fine. Other
In addition, it is more accurate to calculate the bandwidth according to the rising edge time of the measured signal, usually 20%-80% rising edge time, signal frequency Bw=0.4/Tr, and multiply the recommended oscilloscope bandwidth by a coefficient of about 1.4~1.8. . If the bandwidth cannot meet the test requirements, the
The amplitude of the signal is directly reduced, which directly affects the accurate test of the eye height amplitude and rising edge.
In recent years, with the development of technology and the introduction of de-embedding and equalization, this rule is also changing. For example, for PCIE4.0 16.0Gbps, in order to prevent de-embedding from over-amplifying the noise floor of the instrument, the recommended cut-off bandwidth frequency of CTLE and de-embedding given in the PCIE4.0 specification is 20GHz:
Table 3 The recommended cut-off frequency points for de-embedding in PCIE4.0 specification
On the other hand, for the signal source calibration during RX test, in order to ensure accurate calibration of the edge of the signal output by the bit error meter, an oscilloscope with a bandwidth of 25GHz is recommended in the specification for testing:
Taking both into account, the recommended bandwidth for PCIE4.0 in the CEM test is 25GHz:
Sampling rate is another important indicator of the oscilloscope. For today's digital real-time oscilloscopes, the sampling rate must be 2.5 times the bandwidth of the oscilloscope to ensure accurate restoration of the signal. Although the Nyquist sampling theorem points out that 2 times the sampling can restore the signal, the signal targeted by the Nyquist theorem is a sine wave, and today's measured signals are mostly high-speed digital signals.
The other two more obvious indicators that have a greater impact are the noise floor and jitter of the oscilloscope. The inherent jitter of the oscilloscope has a similar impact on the eye diagram test, which will inevitably increase the error in the test of jitter-related items. Since both equalization and de-embedding compensate the signal in the vertical amplitude direction of the signal, the effect and influence superimposed on the inherent jitter needs to be quantitatively analyzed by rigorous mathematical operations. For the HDMI interface that needs to be tested with a probe, when the probe is connected to the signal due to its inherent attenuation characteristics, it will enter the front end of the oscilloscope and ADC for sampling after the signal is attenuated. The oscilloscope will amplify the signal and amplify the noise floor , so the attenuation factor of the probe is also one of the factors affecting the accuracy and margin of the conformance test.
4. The development trend of conformance testing
As an important link before product shipment, since conformance testing plays such an important role in today's various product development and manufacturing, it will inevitably bring a huge workload and burden. Therefore, from the initial USB2.0 and Ethernet10/100/1000 BaseT of hundreds of MBps to today's high-speed serial data standards of tens of Gbps, it has been developing in a simpler, more standardized, and more automated direction. The ultimate purpose And the purpose is to reduce the complexity of testing and improve production efficiency.
It is simpler, mainly reflected in the output of the test pattern. As discussed above, from the initial need for special contract software or changing registers to output test signals to today’s built-in BIST (Built in Self-Test Pattern) test pattern, it has been implemented on both PCIEXpress and USB3.x. For the DisplayPort and Thunderbolt standards, there are special test pattern controllers developed by third parties, such as the DP controller provided by Unigraf and the Thunderbolt controller provided by Wilder.
More standardized , reflected in the definition of the test connection. For example, in the definition of the USB3.0 test method, it was initially defined that the physical cable approved by the association was used to simulate the remote test point, but later, due to differences in the physical cable, the S-parameter model was used to replace the physical cable, which completely eliminated Differences between different connection environments. This method is also applied in HDMI2.0/DP1.4 today. In the PCIE4.0 specification, a similar method is also adopted, but instead of a software S-parameter model, a hardware ISI fixture board provided by the association is used to simulate the entire link. Taking the CEMAdd-inCard TX test as an example, a specially designed An ISI fixture board is used to simulate the additional standard 20dB@8GHz loss:
Figure 6 PCIE4.0 CEM test principle block diagram
Figure 7 PCIE4.0 CEM ISI Fixture Board
This hardware ISI fixture is sold by the PCI-Sig Association and is unique and standard. Whether the S-parameter model method of the software will be used to realize it in the future, of course, this possibility is not ruled out.
The final trend is the growing need for test automation. Due to the complexity of various standards and interfaces, it has brought many troubles to consumers, and also increased the complexity of R&D, design and testing. Therefore, the industry is working hard to promote the adoption of the only Type-C interface, which is supported by standards such as USB, DP, HDMI, and Thunderbolt. The following is a complete test program:
Figure 8 Block Diagram of Type-C Interface Test Scheme
As shown above, use N7015A Type-C fixture and N7018A controller, cooperate with the switch matrix, after all connections are completed, the N7018A control software running on the oscilloscope will automatically set the Type-C Alt Mode, and switch the Type-C interface to USB, DP Or TBT mode, N7018A controller can output LFPS signaling, configure DUT to send out USB3.x standard test patterns, for Thunderbolt and DP, Wilder and Unigraf controllers are required to configure test patterns respectively. The signal under test is connected to the switch matrix from the N7015A fixture, and then connected to the oscilloscope. The oscilloscope will control the switch matrix through the network port to switch signals of different links to the oscilloscope. If you need to test different devices under test, you only need to connect the device to the N7015 fixture.