Broken thoughts:
After writing the FOC code some time ago, the blogger deeply realized that he still has a very big deficiency in the language foundation of Verilog.
Occasionally, when I brush Zhihu while touching fish (touching fish is not the point_(:з)∠)_), I saw an author mentioned that there is a very good open source project Basic Verilog in Github, which contains a lot of commonly used modules As well as script writing, I think it is very necessary to learn, so this article is the first chapter of this series of columns, to record my own learning process!
0 main ideas
Open source library address: https://github.com/pConst/basic_verilog
I plan this column like this, first learn the module part, and write some tb files by hand to give the simulation results. And for some of the special writing, introduce and summarize.
I hope I can stick to it. The following is the article directory of the entire column. I will continue to update it in the future. At present, this column is tentatively scheduled to be updated every two days. I hope everyone will pay more attention!
1 Article Directory
Verilog: [1] Clock frequency divider circuit (clk_divider.sv)
Verilog: [2] Pseudo-random number generator (c_rand.v)
Verilog: [3] Edge detector (edge_detect.sv)
Verilog: [4] Pulse Generator (pulse_gen.sv)
Verilog: [5] Pulse Stretcher (pulse_stretch.sv)