A common method of digital back-end fix hold timing is pad buffer or transfer tree, in fact, there is a method of repair hold: insert lockup latch
Assuming the presence of a larger circuit in FIG hold violation
In order to repair out of this hold, we can insert an active low latch on the data path
After inserting a latch on the data path, since the latch remains transparent during the low level, the original value remains unchanged during the high level, the data corresponding to the half period delay backwards, so that there will be no hold violation the
Here insert the latch is called lockup latch, because its function is like the half cycle of the same data lock
Lockup Latch The most common scenario is hold violation in the scan mode of repair:
Figure above clk1 and clk2 are two independent clock domains, after finishing the latency cts smaller clk1, clk2 a large latency; Since all the scan mode will be strung reg a scan chain, so scan under mode, between R3 and R4 is the need to check timing, but also because the two clock latency difference between the larger, so this path is larger hold violation may occur, in order to repair out of this hold, if we direct it at R3 R4 between the pad buffer, may need to pad a lot of buffer, it is a waste, then you can consider using the lockup latch, the data output from the delay R3 back half cycle, this should hold there would be a problem, some people may worry: this will setup will not cause problems between R3 to R4 do? No need to worry, because in the scan mode clock is slow, clock cycle long enough, unlikely setup violation.
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