Many students ask questions related to the issue of the latch, showing everybody this knowledge is not very understanding, and today we're going to explore.
The figure is not else two code, which code is equivalent to the FIG.
In other words, if the conditions when there is no write else, default is "unchanged" means.
Next, let's talk about how the hardware is to achieve "remains unchanged," the.
Left timing of the timing logic code, the code corresponding to the right is a hardware circuit. Pay special attention to the red line graph, that is to keep constant "feedback." As it can be seen from the figure, when the rising edge of the clock, when the selector signal B is assigned to the result; when the non-rising edge, b has remained the same, thus during the red line is kept unchanged. When a is 0, the selector selects the current results of b, then assign the next rising edge of a clock signal b.
Cited by the visible key, and "unchanged" is to the D register.
As we all know, there is no combination of logic code D register, then it is how to achieve it remain the same? This will be used latch up.
The figure is a combination of the logic code, and the corresponding circuit. In order for the signal b remains unchanged, it is necessary to use one called "latch" devices. When a is 1, b will be equal to 1; and when a is 0, b remains unchanged.
About harm latch, MDY can refer to the "big construe" video, in short, we know that the latches are bad things, try not to have a latch that is in combinational logic, let "if else" conditions Completion.
common problem
Question 1: Is all of the code, if else needs to complement it?
A: As previously discussed, sequential logic may be implemented by registers D "unchanged", it is not required sequential logic complement, only combinational logic only needs.
Question 2: Is it just a combination of logic if else to add, it will not generate a latch up?
A: Not necessarily. The key here is "unchanged", do not be understood from the "code level", but should be understood from the "functional level", to pinpoint in the end there is no "remains unchanged." For example, the following code, although else write up, but the writing is not to write else let b remains unchanged. So it will still be an integrated latch.
Question 3: Is it not written combinational logic else, it will generate a latch?
A: Not necessarily. There is still from whether to include "remain unchanged" function to analyze. The code below, is a 1-bit signal is assumed that only the values 0 and 1. It has covered all cases, there will not be other cases, so the situation will not remain the same, this time it will not generate a latch.
Q 4: case does not write default, whether it will generate a latch?
A: case does not write default, if conditions are not equivalent to write else, its analysis of the situation, like the previous three, the key is that there is no "remain unchanged" function.
Question 5: functional, I must achieve "combinatorial logic remains the same" feature, what to do?
A: Generally speaking, the "combinatorial logic remains unchanged" means "This code" is written combinatorial logic, but need to keep a constant value before the clock, the following code, this demand is normal of.
Solution, still rely on D flip-flop to achieve "remain unchanged" function. Only the wording ALWAYS a sequential logic, the combinational logic into logical clock wording + only, as follows.
Question 6: 5 issue of expansion, I just want to achieve a combination of logic to maintain, and less than one clock cycle.
A: The demand is not normal, FPGA design is not so.
