Cause the core technology has been committed to research chip decryption technology, mainly in the single-chip decryption, decryption chip, MCU decryption IC reverse analysis based.
AT91SAM7XC128 characteristics are as follows:
* integrates ARM's ARM7TDMI ® processor's Thumb ®
- High-performance 32-bit RISC architecture
- High density 16-bit instruction set
- MIPS leader / W
- Embedded ICE in-circuit emulator, Debug Communication Channel Support
Internal high-speed Flash - 256 kilobytes (AT91SAM7X256) at page 1024 of 256 bytes organized
- 128 kilobytes (AT91SAM7X128) at page 512 of 256 bytes organized
- Up to 30 MHz in the worst case single-cycle access
- Thumb prefetch buffer optimization performed at maximum speed command
- Page programming time: 6 ms, including automatic page erase, all erase time: 15 ms
- 10,000 write cycles, 10 years data retention, department lock, flash security bit
- Fast Flash Programming Interface for mass production
maximum access speed Internal high-speed SRAM, single-cycle - 64 kilobytes (The AT91SAM7X256)
- 32 kilobytes (the AT91SAM7X128)
· Memory Controller (MC) - Embedded Flash Controller, suspended state and Misalignment detection
· Reset Controller (RSTC) - Based on reset cell factory calibration down and low power detector
- Providing an external reset signal with the status source forming
· a clock generator (CKGR) - Low power RC oscillator 3 to 20 MHz internal oscillator and the PLL a
· Power Management Controller (PMC) - Power optimization, including slow clock mode (as low as 500 Hz) and Idle Mode
- Four programmable external clock signal
· Advanced Interrupt Controller (AIC) - Maskable alone, eight priority vectored interrupt sources
- Two external interrupt sources and a fast interrupt source, spurious interrupt protection
· debug unit (DBGU) - Line 2 UART interrupt support and Debug Communication Channel, Programmable ICE Access Prevention
· periodic interval timer (PIT) - Programmable counter 20 plus interval counter 12
· window watchdog (WDT) - 12 key protection programmable counter
- Providing a reset signal or an interrupt system
- Counters may stop the processor is in debug state or in idle mode
· Real-time Timer (RTT) - 32-bit free-running counter alarm
- Running the internal RC oscillator
· two parallel input / output controller (PIO) - Sixty programmable I / O lines up to two multiplexed peripheral I / O
- Input change interrupt capability / O line for each I
- Independent programmable open drain pull-up resistor and the output synchronization
· seventeen peripheral DMA controller (PDC) channel
-an Advanced Encryption System (AES) - 128-bit key algorithm, in line with the specifications of FIPS PUB 197
- Buffer encryption / decryption functions with the PDC
· a Triple Data Encryption System (TDES) - Two or triple bond algorithm, in line with the specifications of the FIPS PUB 46-3
- Optimization of the Triple Data Encryption
· a USB 2.0 full-speed (12 megabits per second) Device Port - On-chip transceiver integrated configuration 1352 bytes of the FIFO
· an Ethernet MAC 10/100 Base - T Type - Media Independent Interface (MII) or Reduced Media Independent Interface (the RMII)
- Integrated 28-byte FIFO and DMA dedicated send and receive channels
· a first portion 2.0A and 2.0B CAN controller compatible - Eight mailbox message object fully programmable, 16-bit timestamp counter
· a synchronous serial controller (SSC) - Independently for each clock and frame synchronization signal receiver and transmitter
- I ² S analog interface support, support for time-division multiplexing
- High speed serial data stream of 32-bit data transfer functionality
1.2 Universal Synchronous / Asynchronous Receiver Transmitter (The USART) - Personal baud rate generator, IrDA infrared modulation / demodulation
- Support ISO7816 T0 / T1 Smart Card, Hardware Handshaking, RS485 Support
- Full online support modem USART1
· two master / slave serial (SPI) of the peripheral interface - 8--16 bit programmable data length, four external peripheral chip selects
· a three-channel 16-bit timer / counter (TC) - Three external clock input, two-purpose I / O pins per channel
- Dual PWM generation, capture / waveform mode, up / down counting function
· a four-channel 16-bit pulse width modulation power supply controller (PWMC)
· a two-wire interface (TWI) - Master mode only supports all two wire support Atmel's EEPROM
· an 8-channel 10-bit analog to digital converter, a digital 4-channel multiplex the I / O
* Sum - BA ™ start of assistance - The default boot program
- Interface and SAM - BA GUI
· meet IEEE 1149.1 JTAG boundary scan all digital pins
· 5V tolerant I / O ports, including four large current drive I / O lines for each of up to 16mA
· Power - Embedded 1.8V regulator, up to the core and the outer element of 100mA
- 3.3 VDDIO connected to I / O port supply lines, separate power supply 3.3V VDDFLASH Flash
- 1.8 VDDCORE core power brownout detector
· Fully static operation: 55MHz and up to the worst conditions of 85 ° C 1.65V
* Green 100-pin LQFP package