TMS320F2808 chip basic characteristics:
High-performance static CMOS technology
100MHz (10ns cycle time)
60MHz (16.67ns cycle time)
Low power consumption (1.8V core, 3.3VI / O) designed to
support JTAG boundary scan
IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary-Scan Architecture
High performance 32 the CPU (the TMS320C28x)
16 × 16 and 32 × 32 MAC operations
16 × 16 dual-MAC
Harvard (Harvard) bus architecture
associated calculation
fast interrupt response and processing
the unified memory programming model
efficient code (using C / C ++ and assembly language)
Various types of MCU chip decryption, an application specific IC chip decryption, the PLD chip decryption, decryption SPLD-chip, FPGA / CPLD chip decryption