Even so the epidemic can not escape or school ah! Recently started to learn the basic principles and application of 8051, but as a rookie undergraduate computer science, writing blog also feel powerless, and thus selective binding (piracy, hey) I learned a friend of hardware articles, consisting of a series. A blog is a good means to learn, progress together! Capacity constraints, if something is wrong with the text urge correction!
This series of articles based on 8051, Keil4 / Keil2, and mainly in C and assembler routines to achieve, compiled in part by my friend's big brother (pirate objects). This reference to the contents of the text:
https://blog.csdn.net/qq_43327300/article/details/104698377
First let us introduce hands before we need to understand prior knowledge.
0, MCS-51 series microcontroller Profile
MCS-51 series single-chip was first introduced by intel company (Yes, that intel), then 51 and 52, including sub-series, sub-series contains 51 of the 8051 classic, we now tend to use 8051 said on behalf of MCS-51 series.
To distinguish the various models, MCS-51 series has a clear naming:
Now go buy related development boards typically buy STC89C52 other models, the author of the hands of the development board is STC89C516 is a more common type of derivative, as these devices basically the same instruction set, thus learning are not very different.
Next, in this chapter show a more typical 8051 based on MCS-51 series microcontroller introduced introduced.
1, MCS-51 series single-chip hardware configuration
1.1 Internal Structure
There consisting of microcontroller hardware
1, 1 of 8bit CPU
The 2,1-chip oscillator and clock circuit
3, a program memory, 4KB mask ROM, for storing programs, tables, and the raw data
4, a data memory
5,64KB bus expansion controller (which is often said external RAM)
6,4 8-bit parallel I / O ports (P0, P1, P2, P3)
7, a full duplex serial interface
8,2 sixteen-bit timer / counter
9,5 interrupt sources
Program and data memory are separate, consistent Harvard architecture.
1.2 External Pin Function
8051 total external pin 40, wherein the parallel I / O port accounted for 4x8 = 32 th
1, the power supply pin
VCC: Power chip, + 5V
VSS: Ground
2, the clock pin
XTAL1, XTAL2: an inverting input terminal and output terminal of the crystal oscillation circuit
Then tell a comparison, quiteimportantThe timing of the content --8051
Details we read it, I am here to leave a textbook example we Ye Hao understand binding
1T = 6T state machine cycle S = 12T clock cycle (oscillation) period P
Example: Let the application microcontroller crystal frequency is 12MHz, and asked how much machine cycle?
Solution : obtained from the known crystal frequency of 12MHZ, the reciprocal of the frequency period
Therefore, 1 / T = 12MHz => T = 1 / 12M (s)
Machine cycle = 12x1 / 12M = 1 / 1M (s) = 1us
Similarly crystal frequency is 24MHz, the machine cycle is 0.5us
3, the control pin
RST / VPD: a reset signal input / standby power input terminal
EA / VPP: internal and external ROM selection terminal / power-chip program EPROM
ALE / PROG: the address latch enable / chip EPROM programming pulses
PSEN: external ROM 读选 communication No.
2, MCS-51 series single-chip memory configuration and function
2.1 Types of memory
A ROM : for storing a program, information is retained after the power failure
The RAM : for storing data, the information disappears after a power failure, the outer slices inner sheet
2.2 the address storage unit and a storage unit
The memory is a large numberregisterThereof, wherein eachregisterCalled aThe storage unit. It can store a binary code. A code consists of a number of bits ( 'bit ) composed of 8051 microcontroller arithmetic unit is eight, i.e., a byte ( Byte ), may also be referred to as a size of the memory capacity of the memory in bytes ( B ) units, 8051 the MCU Have4KB of program memory, That is to say 8051 microcontroller's internal program memory can be stored4x1024 a Byte
2.3 reading memory cells, the write operation
Read (1) memory
A read operation, will not destroy the original contents of the unit data corresponds to copy only
Write operation (2) memory
Write operation, or refresh to change the original contents of the cell, equivalent to the original content to be covered
2.4 MCS-51 series single-chip storage configuration
8051 memory organization structure can be divided into three different storage
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64KB program memory ( ROM ), comprising an outer sheet and inner sheet ROM ROM
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64KB external data memory ( outside the RAM )
-
256B internal data memory ( within the RAM ) (including special function registers)
(1) 8051 a program memory (ROM)
Address range: 0000H FFFFH ~ , a total of 64KB
Low stage 4KB: 0000H ~ 0FFFH
8051 and 8751 in the sheet, 8031 in the chip. High section 60KB: 1000H ~ FFFFH . In the outer sheet.
Write ROM with MOVC instruction, is a control signal PSEN and EA .
(2) 8051 data memory (RAM)
The data memory is divided into an outer RAM and the RAM
External RAM address range: 0000H FFFFH ~ co 64K
The RAM address range: 00H FFH ~ co 256B , is divided into two parts:
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An internal memory space, address 00H ~ 7FH ( low 128B is )
-
Special function registers, address 80H ~ FFH ( high 128B is )
Access chip RAM with the MOVX command to access on-chip RAM with the MOV instruction
2.5 8051 within data memory space (128B is low)
(1) working register area (00H ~ 1FH)
Action: dedicated to the working register instructions that, generally read and write speed than the RAM faster, instruction bytes are shorter than normal direct addressing instructions, also having an indirect addressing function (only R0, R1 can)
The working register is divided into four regions: the region 0,1,2,3. Each zone has eight registers: R0 ~ R7
(2) bit addressing zone (20H ~ 2FH)
Action : not only address bytes, and each byte address also bit address , bit manipulation can be performed
(3) a data buffer (30H ~ 7FH)
Action : used to store various data and intermediate results, the data buffer functions. Stack generally open in the region
00H ~ 7FH is general user operable region
2.6 Special Function Registers (128B is high)
21 is special function registers, wherein the address is the last byte0hor8HEvery register has a bit address, you canBit operating
The SFR
Occupancy address byte: 80H ~ FFH
Bit addressable device: byte address which may be divisible by 8, i.e. Mentioned above 0H, 8H end
Dedicated registers:
A、B、PSW、DPTR、SP
I / O interface registers:
P0、P1、P2、P3、SBUF、TMOD、TCON、SCON…
(1) accumulator Acc
The most common register, all the operation type command must use it. Accumulator bit in the instruction mnemonic A, with its own Zero Z, if A = 0 then the Z = 1; if A! = 0, then the Z = 0. The flag is used to program the branch judgment condition
(2) B register
80C51 , the B register must be used when doing multiplication and division, multiplication and division when not, can be used as a general register
(3) The program status word PSW
(4) SP Stack Pointer
After use again perfect
(5) the data pointer DPTR
Into the DPL (lower 8 bits) and the DPH (upper 8 bits) of two registers used to store the 16 -bit address value.
2.7 Parallel I / O port
Four 8-bit bidirectional parallel port: P0, P1, P2, P3
P0, P1, P2, P3 port corresponding to the four data latch: P0, P1, P2, P3 , corresponding to the internal RAM address of 80H, 90H, A0H, B0H , access I / O port bit address , when the microcontroller is reset when, P0 ~ P3 contents of the latch are 1
For convenience of description we have introduced in the order of P1, P2, P3, P0's.
(1) P1 port
P1 port only simple bi-directional I / O functions, each mouth is the most simple one.
When we achieve an output state illustrated in Figure 17:
Internal bus input to the D flip-flop 0, V1 is turned on by the high level, VCC to ground, and thus the external output 0, 1 is input to the D flip-flop in the same way bus, V1 off by a low level, P1 port to output a high level.
When receiving the data port P1 we refer to the diagram:
We want to first have to make the FET off when the port P1 receives the data, thus requiring a high level first output enable input of D flip-flops is high, so that the level of level signal successfully reached the bus.
Thus before the input data must first output a high level!
(2) P2 port
First, we can achieve with the port P1 P2 port functions:
When the CPU 1 is issued a control signal to the multiplexer MUX address lines inside the guide, so as to use a high port P2 eight address lines.
Driving capability port P2 four gates LSTTL
(3) P3 port
P3 having all the features (shown below) as well as a second feature described in our previous P1.
When P3 the second function port remains high, P3 port as a general purpose I / O using the port, and function P1 same
(4) P0 port
P0 is a tri-state bidirectional port as an address / data time-multiplexing port, but also as a general purpose I O port P1 is the interface functions /.
When the control signal is low do general purpose I / O pins.
Due to its lack of pull-up resistor, an external pull-up resistor to a high output.
When the control signal is high, P0 port as the address / data time-multiplexed bus.
3, MCS-51 series microcontroller reset mode
(1) Reset condition
Reset (RST) pin (pin 9) plus a duration of two machine cycles of high
If the device clock frequency is 12MHz , the machine cycle is 1us , then we need to continue 2us time or more.
(2) the internal register after reset state
