(1) in the following table
(2) Detailed Description
PCIE protocol has now grown to 1.0, 2.0 and 3.0 versions, the transmission rate is not the same.
PCIe is a serial bus, a line PCIe1.0 bit transmission rate of 2.5Gb / s, the physical layer encoding 8/10, i.e., 8 bits of data actually to be transmitted on a physical line is 10 bits, thus:
Bandwidth PCIe1.0 x 1 = (2.5Gb / s) / 10bit = 250MB / s
This is the single Lane bandwidth, there are several Lane, then the entire bandwidth is 250MB multiplied by the number of Lane.
PCIe2.0 turn online bit transmission rate on the basis of PCIe1.0 doubled to 5Gb / s, using the same physical layer coding 8/10, so:
Bandwidth PCIe2.0 x 1 = (5Gb / s) / 10bit = 500MB / s
Similarly, how many Lane, the bandwidth is 500MB / s multiplied by the number of Lane.
PCIe3.0 bit transmission rate of the line is not on the basis PCIe2.0 double than 10Gb / s, but 8Gb / s, but the physical layer is used for data transmission 128/130 coded, so that:
Bandwidth PCIe3.0 x 1 = (8Gb / s) / 8bit = 1GB / s
Similarly, how many Lane, the bandwidth is 1GB / s multiplied by the number of Lane.
As a result of encoding 128/130, 128-bit data, 2bit only additional overhead, the effective data transmission rate is increased, although the line bit rate is not doubled, but the effective data bandwidth or on the basis PCIe2.0 do the double.
It is worth mentioning is calculated taking into account the above data bandwidth is 8/10 or 128/130 coding, therefore, we calculate the bandwidth at the time, no need to consider the issue of the coding line.
Different single-channel and SATA, the PCIe connector by increasing the number of channels can be extended bandwidth, very flexible. The more channels, the faster. However, the more the number of channels, the higher the cost, take up more space, there is more power. Therefore, the number of channels, should be a comprehensive consideration between performance and other factors.
PCIe is a PCI development from over, PCIe of "e" is short for express, fast meaning. PCIe how it can be faster than PCI, PCIe physically transport because, essentially different with PCI. PCI uses parallel data transfer, while PCIe serial transmission is used. PCI parallel bus, a single clock cycle may be transmitted 32bit or 64bit, how would you not be transmitted over a single serial bus clock cycle a data bit of it. In the actual clock frequency is relatively low, several bits can be transmitted as parallel simultaneously, indeed rate faster than serial. With the development of technology, more and faster data transmission rate requirements, requires faster clock frequency, however, the parallel bus clock frequency is not able to think fast fast. As shown below:
At the transmitting end, the data spread out along a clock (first clock rising edge on the left), the receiving end, the received data in the next clock edge (the right edge of the second clock). Thus, to be able to correct the data collected at the receiving end, the required clock period must be greater than the data transmission time (from sender to receiver). Limited by the data transfer time (time further increases as the length of the data line is increased), so the clock frequency can not be made too high. Further, when the clock signal is transmitted on line, also there is a phase shift (clock skew), impact receiving end of data acquisition.
PCIe serial bus for data transfer does not have these problems. It is not the external clock signal, which clock information is embedded in the data stream encoded by 8/10 encoding or 128/130, the receiving side can recover the clock information from the data stream inside, and therefore, it is not a limiting line data transmission time, you How long wires are no problem, you fast data transmission frequency is no problem; there is no external clock signal, naturally there will be no so-called clock skew problem.
