I. Introduction
Years of working as a systems engineer, will inevitably have to do two things: training of new employees and new employees assigned to the task. For those students just out of school, usually at the beginning is always assigned some very simple tasks, such as GPIO driver, LED driver. Often about the chapter CPU datasheet GPIO or IO ports are relatively simple, ideal for engineers joined the line. Although GPIO subsystem associated hardware is relatively simple, not complex protocols, however, for software abstraction, its layered software idea is that each embedded software engineers need to master the content.
I prefer to use this system GPIO GPIO driver name instead of the name, GPIO driver contains only pin signal status control and read the contents, and the system includes a GPIO pin multiplexing, pin configuration, GPIO control, GPIO interrupt control and so on. This article is based on 3.14 kernel as an example, about the software framework GPIO linux kernel in the system.
Two, GPIO related hardware What are the differences
Embedded engineers always have to deal with a variety of target board, GPIO on each target board there is always different, for example:
1, and the connection of different CPU
For ARM embedded hardware platform, SOC itself can provide a lot of IO port, GPIO controller in the SOC is connected to the CPU via the SOC bus (AMBA). For embedded systems, in addition to IO port SOC, a number of peripheral chips may also provide IO port, for example:
(1) Some key controller chip, codec chip or PMU provides I / O port
(2) Some special IO expander chip 16 can be extended or 32 GPIO
From a hardware perspective, such as those provided by the IO IO SOC and is completely different, CPU, and IO expander via the I2C (there may be other types of like SPI bus) connection, in this case, access outside these GPIO SOC an I2C operation, controls the operation of the GPIO write only register the SOC. Do not underestimate this difference, write a SOC memory map registers very quickly, but is operated by I2C IO is not so fast , even if the bus is busy it is possible to block the current process, in this case, the kernel synchronization mechanisms must be the difference ( if the operation could lead to GPIO sleep, then the synchronization mechanism can not be used spinlock ).
2, different access methods
IO expander Access Controller GPIO outside the SOC and the SOC chip-chip course not the same, but, even if the SOC is within GPIO Controller chip, different chips ARM, which is not exactly the same access mode, for example: Some of the SOC GPIO register provides a controller to control the output level. Write to register 1 is set high, write 0 is set low to register. However, some of the SOC GPIO controller provides two registers to control the output level. Is set high to write a one of the registers, a write is set low to another register.
3, different configurations
Even with the same hardware (e.g., a paragraph use the same SOC), GPIO on different systems with different hardware configurations. Disposed on a system input, may be configured to output on another system.
4, GPIO different characteristics. These features include:
(1) whether it can trigger an interrupt. For a SOC, it does not support all the IO port interrupt function, some processors may have only one or two GPIO interrupt function.
(2) if it can trigger an interrupt, then the GPIO is able to wake up the CPU from a sleep state
(3) there are some software controlled pull-up or pull-down resistor characteristics, some GPIO does not support this feature. In the set input when GPIO can be set debouce some algorithms, and some can not.
5, multi-multiplexing
Some GPIO is simply appears as a GPIO, GPIO some other multiplexing function. For example GPIO on IO expander can only be GPIO, but one GPIO on the SOC in addition to doing normal IO pin foot, also can be the SPI clock signal line.
Third, the hardware functional classification
ARM based SOC datasheet of the total is called a chapter GPIO controller (or I / O ports) to describe how to configure the section, using the SOC pins. While the GPIO controller hardware description of a large number of full description of the register, but the functions of these registers roughly divided into the following three categories:
1, some hardware logic and IO port function setting itself relevant, we call this HW block as a pin controller. Software can be implemented by setting this register pin controller hardware unit:
(1) pin function. For example, the I / O pin is common to a GPIO pins or some special functions (for example, a CS signal memeory bank).
(2) Characteristics of the pin configuration. For example, pull-up / down resistors to set, drive-strength settings and the like.
2, if a group is configured to GPIO SPI, then these pins are connected to the pin SPI controller, if GPIO configured, the control of these pins is GPIO controller. By accessing GPIO controller registers, the software can:
(1) arranged direction of GPIO
(2) If the output can be configured high level or low level
(3) If the input level state may be acquired on the GPIO pins
3, if a group gpio interrupt controller function, although the control I / O ports in the datasheet register section as described, but in practice these have been organized into a GPIO interrupt block controller hardware, which is more like a GPIO type interrupt controller, interrupt controller by accessing the GPIO type of register, the software can:
(1) interrupt enable and disable (mask and unmask)
(2) trigger
(3) Clear the interrupt status
Fourth, how to cover up the difference through hardware abstraction software
Traditional GPIO driver is responsible for controlling the above three categories, and the new linux kernel is used in the three GPIO subsystem software module corresponding to the above three types of hardware features:
(1) pin control subsystem. Software driver pin controller hardware subsystems.
(2) GPIO subsystem. Driver GPIO controller hardware, software subsystems.
(3) GPIO interrupt chip driver. This interrupt subsystem as a module in a drive module present in the underlying hardware. This article describes the former two software modules, specific GPIO interrupt chip driver and interrupt subsystem, please refer to this site to other related documents.
1、pin control subsystem block diagram
The following figure depicts a block diagram of the pin control subsystem:
The bottom of the pin controller driver is hardware-related module initialization time will be registered pin control device to pin control core module (by pinctrl_register this bootom level interface). pin control core module is a hardware-independent module, which abstracts all hardware characteristics of the pin controller, the user only from the (respective driver pin control subsystem is the user) the angle of top level interface functions are given, so that each driver does not need to concern pin controller of relevant content underlying hardware.
2、GPIO subsystem block diagram
The following figure depicts a block diagram of the GPIO subsystem:
Basically this software framework diagram and pin control subsystem is the same, its software abstract ideas is the same, of course, the specific implementation of its interior is not the same, we will describe in a future article.
Original link:
http://www.wowotech.net/io-port-control.html
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