One of the GPIO systems in the linux kernel (1): software framework
Author: linuxerPublished in: 2014-7-21 14:40 Category: GPIO Subsystem
I. Introduction
As a system engineer who has worked for many years, it is inevitable to do two things: train new employees and assign tasks to new employees. For those students who have just come out of school, some very simple tasks are usually assigned at the beginning, such as GPIO driver, LED driver. Often the chapters about GPIO or IO ports in the CPU datasheet are relatively simple, which is very suitable for engineers who are just starting out. Although the hardware related to the GPIO subsystem is relatively simple and there is no complicated protocol, for software abstraction, its hierarchical software idea is what every embedded software engineer needs to master.
I prefer to use the name GPIO system instead of GPIO driver. GPIO driver only includes pin signal status control and reading, while GPIO system includes pin multiplexing, pin configuration, GPIO control, GPIO interrupt control, etc. This article mainly uses the 3.14 kernel as an example to describe the software framework of the GPIO system in the Linux kernel.
2. What are the differences between GPIO related hardware
Embedded engineers always have to deal with various target boards, and the GPIOs on each target board are always different, for example:
1. The connection with the CPU is different
For the ARM embedded hardware platform, the SOC itself can provide a large number of IO ports, and the GPIO controller on the SOC is connected to the CPU through the SOC bus (AMBA). For embedded systems, in addition to the IO port of the SOC, some peripheral chips may also provide IO ports, for example:
(1) Some key controller chips, codecs or PMU chips will provide I/O ports
(2) Some dedicated IO expander chips can expand 16 or 32 GPIOs
From a hardware point of view, these IOs are completely different from those provided by the SOC. The CPU and IO expander are connected through I2C (and possibly other types of bus such as SPI). In this case, access to GPIO outside these SOCs The operation of I2C is required, and the operation of writing registers is only required to control the GPIO on the SOC. Don't underestimate this difference, writing a register of a SOC memory map is very fast, but it is not so fast to operate IO through I2C. Even if the bus is busy, it may block the current process. In this case, the kernel synchronization mechanism must have some The difference (if the operation of GPIO may cause sleep, the synchronization mechanism cannot use spinlock).
2. Different access methods
The access of the GPIO controller on the SOC chip and the IO expander off the SOC chip are of course different. However, even if they are the GPIO controller on the SOC chip, different ARM chips have different access methods. For example: some SOC GPIOs The controller will provide a register to control the output level. Writing a 1 to a register is set high, and writing a 0 to a register is set low. But the GPIO controller of some SOCs will provide two registers to control the output level. Writing a 1 to one of the registers is set high, and writing a 1 to the other register is a set low.
3. Different configuration methods
Even if the same hardware is used (for example, the same SOC is used), the GPIO configuration on different hardware systems is different. Configured as an input on one system, may be configured as an output on another system.
4. GPIO characteristics are different. These features include:
(1) Whether the interrupt can be triggered. For a SOC, not all IO ports support interrupt function, and some processors may only have one or two GPIOs with interrupt function.
(2) If an interrupt can be triggered, whether the GPIO can wake up the CPU from the sleep state
(3) Some have the feature of software-controlled pull-up or pull-down resistor, and some GPIOs do not support this feature. When set as input, some GPIOs can set the algorithm of debouce, while others cannot.
5. Multifunctional reuse
有的GPIO就是单纯的作为一个GPIO出现，有些GPIO有其他的复用的功能。例如IO expander上的GPIO只能是GPIO，但是SOC上的某个GPIO除了做普通的IO pin脚，还可以是SPI上clock信号线。
三、硬件功能分类
ARM based SOC的datasheet中总有一个章节叫做GPIO controller（或者I/O ports）的章节来描述如何配置、使用SOC的引脚。虽然GPIO controller的硬件描述中充满了大量的寄存器的描述，但是这些寄存器的功能大概分成下面三个类别：
1、有些硬件逻辑是和IO port本身的功能设定相关的，我们称这个HW block为pin controller。软件通过设定pin controller这个硬件单元的寄存器可以实现：
（1）引脚功能配置。例如该I/O pin是一个普通的GPIO还是一些特殊功能引脚（例如memeory bank上CS信号）。
（2）引脚特性配置。例如pull-up/down电阻的设定，drive-strength的设定等。
2、如果一组GPIO被配置成SPI，那么这些pin脚被连接到了SPI controller，如果配置成GPIO，那么控制这些引脚的就是GPIO controller。通过访问GPIO controller的寄存器，软件可以：
（1）配置GPIO的方向
（2）如果是输出，可以配置high level或者low level
（3）如果是输入，可以获取GPIO引脚上的电平状态
3、如果一组gpio有中断控制器的功能，虽然控制寄存器在datasheet中的I/O ports章节描述，但是实际上这些GPIO已经被组织成了一个interrupt controller的硬件block，它更像是一个GPIO type的中断控制器，通过访问GPIO type的中断控制器的寄存器，软件可以：
（1）中断的enable和disable（mask和unmask）
（2）触发方式
（3）中断状态清除
四、如何通过软件抽象来掩盖硬件差异
The traditional GPIO driver is responsible for the above three types of control, while the GPIO subsystem in the new linux kernel uses three software modules to correspond to the above three types of hardware functions:
(1) pin control subsystem. The software subsystem that drives the pin controller hardware.
(2) GPIO subsystem. The software subsystem that drives the GPIO controller hardware.
(3) GPIO interrupt chip driver. This module exists as a low-level hardware driver module in an interrupt subsystem. This article mainly describes the first two software modules. For the specific GPIO interrupt chip driver and interrupt subsystem, please refer to other related documents on this site.
1、pin control subsystem block diagram
The following figure describes the block diagram of the pin control subsystem:
The underlying pin controller driver is a hardware-related module. During initialization, the pin control device will be registered with the pin control core module (through the bootom level interface of pinctrl_register). The pin control core module is a hardware-independent module, which abstracts the hardware characteristics of all pin controllers, and only provides the top level interface functions from the perspective of the user (each driver is the user of the pin control subsystem), so that each driver does not need to pay attention to The underlying hardware-related content of the pin controller.
2、GPIO subsystem block diagram
The following figure depicts the block diagram of the GPIO subsystem:
Basically, the software framework diagram is the same as the pin control subsystem, and the idea of its software abstraction is also the same. Of course, its internal specific implementation is different, which we will describe in subsequent articles.