About automated Makefile variables

Makefile automation variable in the management of a large number of source files is very efficient, it can avoid writing too cumbersome Makefile managing large projects.

 

The following is a commonly used automated Makefile variables and their interpretation.

 

$@

 It represents a collection of object files, separated by a space. This variable will in turn generate the target output target file.

Example:

OBJ=first second third

$(OBJ):
    @echo $@

 The output is:

first
second
third

 

$^

Represents the target depends collection of files, separated by a space. This variable will output all dependent files when generating target.

Example:

OBJ=first second third
SRC=one two three

$(OBJ):$(SRC)
     @echo $^

 The output is:

one two three
one two three
one two three

 

$<

It represents a target-dependent file file.

Example:

OBJ=first second third
SRC=one two three

$(OBJ):$(SRC)
    @echo $<

 The output is:

one
one
one