Stop and Ignore Pins
Stop pins and ignore pins both stop the clock tree specification process from tracing beyond a pin. A stop pin is treated as a sink to be balanced whereas an ignore pin is not balanced. For details about stop and ignore pins, see the Clock Tree Sink Pin
Types section.
Macro Clock Input Pins
The clock input pins of macros (.lib model) must usually be earlier than other sinks, which means they will have a lesser clock arrival time to take account of the internal clock path inside the macro. If this is represented by a pin specific network latency,
set_clock_latency, command in the SDC timing constraints then the automatically-generated clock tree specification will take this into account. This is discussed further in the Network Latencies section.
If the clock offset at a macro clock pin is not captured in the timing constraints, then you must add this. For example:
set_ccopt_property –pin mem1/CK insertion_delay 1.2ns
Note that the property setting is the delay to be assumed inside the macro. Positive numbers will reduce the clock arrival time at the pin, negative numbers will increase it. This is illustrated in the following diagram, where X represents the property setting value.
Pin Insertion Delay
It is possible to set a pin insertion delay at any clock sink to adjust the skew of the sink relative to other sinks without such a setting. This can be used to implement manual or preCTS useful skew. Note that setting a pin insertion delay on large number of pins is not recommended and may increase clock area and power.
Architectural Clock Gates
An architectural clock gate is a clock gate typically very early (small insertion delay) in a clock tree that is used to enable and disable entire functions or logical partitions of a design. The flops controlling such a clock gate may also need to be scheduled early to avoid setup slack violations at the clock gate enable input. This can be achieved by adding an additional skew group to balance the flops with the clock gate. For an example of this, refer to the example, Balancing flops with a clock gate, in the Modifying Skew Groups section. Such additional configuration for architectural clock gates is frequently recommend with CCOpt, and will be essential for timing closure with CCOpt-CTS.
Restricting CCOpt Skew Scheduling
CCOpt will initially compute the maximum insertion delay over all skew groups. By default, CCOpt skew scheduling is restricted
such that the insertion delay of any sink may not exceed some factor multiplied by the initially computed maximum insertion delay. This factor is set by the property, auto_limit_insertion_delay_factor, which defaults to 1.5. This permits useful skew scheduling to increase the global maximum insertion delay by up to 50%. Useful skew scheduling is unrestricted by how much it can decrease the insertion delay to a sink.
To restrict the skew of a given skew group in CCOpt set the target_skew property on the skew group and set the constrains property of the skew group to include the keyword ‘ccopt’. For syntax details, see the Defining Skew Groups section. For example, to place a hard limit on the skew of all skew groups to 400ps, irrespective of the impact on timing closure, use the following commands:
foreach sg [get_ccopt_skew_groups *] {
set_ccopt_property target_skew 400ps –skew_group $sg
set_ccopt_property constrains ccopt –skew_group $sg
}
Method
The recommended method for setting up CCOpt or CCOpt-CTS on a new design is to use the following steps:
- Configure and create the clock tree specification as per the Quick Start Example and configuration instructions above.
- Before invoking the ccopt_design command use the CCOpt Clock Tree Debugger in unit delay mode to inspect the clock tree.
This will permit examination of the clock tree structure. For more information, see the Unit Delay section. - Invoke only the clustering step of CCOpt or CCOpt-CTS which performs buffering to meet design rule constraints but does not
perform skew balancing or timing optimization. Check the maximum insertion delay path looks sensible in the CCOpt Clock
Tree Debugger. For designs with narrow channels, many blockages, or complex power domain geometries this is a good time
to check for large transition violations caused by floorplan issues. The screenshot, “Cluster Maximum Insertion Delay”, below
shows the placement view (left) and the CCOpt Clock Tree Debugger view (right) with the maximum insertion path delay
highlighted in green. - For a CCOpt flow with a simple clock tree, for example a CPU core, switch to using full ccopt_design. For a design with a
complex clocking architecture consider using trial mode, which will perform clustering and then balancing using virtual delays.
The trial balancing can be inspected to look for large skew or insertion delay increases due to conflicting skew group
constraints. The design can be timed using timeDesign -postCTS to check for large timing slack violations, for example, due to
incorrect balancing constraints. Virtual delays will appear in timing reports as additional arrival time increments. - Run full ccopt_design. Inspect the log file for errors and warnings. For CCOpt, a summary table of timing slack and other
metrics at each stage of the ccopt_design internal flow is reported. - For CCOpt, check the worst chain report in the log. Note that there may be multiple worst chain reports in the log. It is
recommend to look at the worst chain report after the last occurrence of skew adjustment before any re-clustering steps in the
log, this is usually the second last chain report. This report will indicate if useful skew scheduling has hit constraint limits that
are limiting optimization. For more information on the worst chain report, see the Worst Chain section . - Report on clock trees and skew groups. For example, it is recommended to check skew group maximum insertion delay and
clock tree area even if setup timing slack is closed. For more information, see the Reporting section.
As mentioned above, CCOpt and CCOpt-CTS can be configured between cluster, trial, or full mode using the balance_mode
CCOpt property.
set_ccopt_property balance_mode cluster | trial | full
ccopt_design -cts
The default is full mode. The concepts of clustering and trial virtual delay balancing are detailed further in the Graph-Based
CTS section.
