Author | Wu Xingling
Exhibition | CSDN (ID: CSDNnews)
Today we are living everywhere is inseparable from the chip technology: mobile phones, computers, home appliances, trains, robots can say ...... chip is the information industry "heart." In fact, as early as 2010, the "decision to accelerate the development of strategic emerging industries" that will inherit circuit industry as an important part of a new generation of information technology industry is a strategic emerging industries in the future focus on the development of the country.
It may have been, high technology and capital threshold chips , yet at the time did not make a prototype chip has required tens of millions of dollars in investment, the road is not easy to build the core.
How to reduce the capital investment made core ? We need from technology to reduce the threshold for chip design.
According to Ali Dharma Institute released the "2020 Top Ten Technology Trends Dharma hospital," predicted a "core particles" (Chiplet) modular design approach is becoming the new industry trends. This method by decomposition of complex functions, the development of a variety of specific functions having a single "core particles", such as for data storage, computing, signal processing, data flow management and other functions. These core particles using a modular assembly of different functions, different computer elements integrated on a silicon chip, to achieve a smaller and more compact computer systems architecture. Thus, the threshold can be reduced by the modular design of chip design.
So this technology will bring what kind of impact the current chip design? Based on this, we explore what it?
Different processes of chip costs a huge difference
IBS company once Apple's case, comparing the cost of different production processes of transistors per chip Apple: In 16nm process, $ 498 / one billion transistors in 7nm process, only $ 2.65 / 1 billion transistors. From the design costs, the process node 28nm, single-chip design cost about $ 041 million, for process nodes is 7nm, design costs are quickly rise to about $ 222 million. Cost and use of early maturing and use of a difference of more than doubled. [1]
Node cost in chip design process in each period [1]
According to Dharma Institute said that with the chip manufacturing process from 10nm down to 7nm, then have to be further reduced to 5nm, every process to reduce costs and development time required are increased dramatically.
So we need to find a new chip development model, lower cost and faster development of chip , chip modular design is probably one of the ideas.
Exploring Solutions
Bodhidharma hospital said that before designing a SoC, need to buy a different IP from IP vendors, including IP soft core or hard core IP, combined with their own research and development of modules, grouped into a SoC, the chip is completed in a manufacturing process node complete process design and production. Future may not be made by individually packaged chips, but on-chip networks interconnected into a larger core particle made of silicon. The modular technology allows chip developers to implement like building blocks "assembly" chip.
VeriSilicon founder & chairman and president, Computer Engineering, University of California, Santa Cruz tenured professor, former chairman and chief technology officer Celestry Wayne Dai in the "historic opportunity and the core particles embedded artificial intelligence" has been talked about, the core tablets chip die form is provided, rather than the form of software. The core particles provided with short development cycle pattern, design flexibility, low cost characteristics; it may be a different process nodes, different materials, different functions, different suppliers of commercial package together with a specific function.
Major companies and organizations are exploring innovative chip R & D program:
2017, CHIPS (Common Heterogeneous Integration and IP Reuse Strategies, generic heterogeneous integration and IP reuse strategy) project was established, its vision is to create a diverse ecosystem discrete core particles of the appropriate node manufacturing, and the development of modular chip module series assembled into larger design tools, standards and integrated IP blocks. The project members include Intel, Micron, Synopsys, Candence, Northrop Grumman, Lockheed Martin, Boeing, University of Michigan, Georgia Tech, North Carolina State University.
2018年10月，7家公司成立ODSA（Open Domain-Specific Architecture，开放专用域架构）组织，到2019上半年已超50家，其目标是制定芯粒开放标准、促进形成芯粒生态系统、催生低成本SoC替代方案。
2019年，英特尔推出Co-EMIB技术，其能将两个或多个Foveros芯片互连。
2019年6月，台积电发布自研的芯粒“This”，其由两颗7nm工艺的小芯片组成，每颗小芯片包含4个 Arm Cortex- A72处理器，芯片间通过CoWoS中介层整合互连。
清华大学长聘教授尹首一表示，开源IP核、Chisel语言以及芯粒技术在不同层次上成为实现芯片敏捷开发的使能技术。开源IP核降低了芯片设计的进入门槛，Chisel语言提高了硬件抽象层次，而芯粒则为系统级芯片设计提供了崭新途径。尤其是未来随着异质集成、三维集成等技术的成熟，摩尔定律将在全新维度上得以延续。
除此以外，达摩院表示，近年来，以RISC-V为代表的开放指令集及其相应的开源SoC芯片设计、以Chisel为代表的高级抽象硬件描述语言和基于IP的模块化模板化的芯片设计方法，推动了芯片敏捷设计方法与开源芯片生态的快速发展，越来越多芯片企业开始尝试开源硬件架构进行设计。
技术挑战
在我们探索模块化芯片设计的道路上，阿里平头哥副总裁孟建熠提出目前模块化芯片设计研发上遇到的难题：模块化设计技术还在发展中，如今仍还没有非常好的模块架构整体解决方案，未来芯粒之间的通信技术、芯片的散热技术和封装技术都需提升。
据孟建熠透露，目前阿里巴巴旗下的独立芯片公司平头哥正在进行芯粒及其封装方面的应用研究，基于一站式芯片设计平台——无剑平台的实践经验，将有助于阿里更好地洞察场景需求、培育芯片生态、探索模块架构解决方案。
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