What is SystemC
First, SystemC is not a new language, but on library C ++ development; therefore, you are familiar with C ++ knowledge can be used in the SystemC modeling; in theory, SystemC library and common boost library does not have any substantial difference . In addition, it also tells us that only support a C ++ environment, we can be SystemC modeling and simulation, without any other tools, which compared to other software and hardware modeling language, the required environment is extremely simple.
Note: The most common hardware description language Verilog, simulation tools it needs to support the simulation, such as VCS, modelsim etc, they are expensive EDA tools, and use complex.
Secondly, SystemC is owned by the organization Accellera open source library that uses the Apache 2.0 open source license; Apache2.0 protocol is a license for commercial use friendly, so, regardless of the user with the development of a commercial product is, you can rest assured that use, do not worry violations.
However, SystemC is used to do it? SystemC naming has demonstrated its use, it is a system modeling language; we often use to describe the complex system of things, a computer, a chip, a company can be called a system. System has many features, such as at work, etc. modularity, parallelism, communication mechanisms, the rule. In an example a computer, CPU, GPU, memory, a display, etc. are separate modules, each complete their tasks; they always work in parallel, but also communicate with each other via the interface. How to model a system? Native programming language is executed serially, not modeling parallel systems; even if you are modeling a system, but in the end have to run simulation on the CPU, the CPU always serial execution. We know that the hardware is a combination of large number of parallel execution unit must be able to support the parallel operation of analog; SystemC is born to do, provided strong support for the hardware and software system modeling.
Summary: SystemC is a support system modeling of open source C ++ library;
SystmeC role
Modern chip always includes hardware and software, firmware or software part can be driven; chip market is a very competitive market, almost all of the company's chip products have strict time planning; how to get products to market as quickly as possible, how to reduce product bug the problem is almost all chip companies have to face. SystemC allows parallel development of hardware and software, speed up time to market.
As shown below left, the traditional design process prior to FPGA prototype out almost no communication between hardware and software development; only after a long "design - verification - General" after the process (usually a few months), the software can tested on FPGA platform your code, because there is no platform software test design, test at this time there must be a lot of error that you need to modify hardware or software, and re-iterated that this will waste a lot of time. In the computer field, there is a wisdom: The earlier bug, the smaller the loss. Obviously, the traditional design flow and this does not match the target.
, Before the hardware and software design, to develop below right SystemC abstract model (e.g., model TLM), and then convert this hardware sector the RTL model, software development software on this sector model. In this way, any errors in hardware and software can be found and fixed as soon as possible, saving development time.
FAQ 1: SystemC model development also increases the design process is not time yet?
A: Yes, SystemC model development does take time; however, because C ++ is a high-level language, and the model here does not require precise clock to level, only needs to reach TLM level, so compared to the difficulty of development and design verification of hardware and software development for very low, the time-consuming and can be ignored.
FAQ 2: Why not develop on RTL software?
A: First, wait until the RTL run out of a need for a very long time; secondly, RTL simulation speed of at least 100x times slower than the speed of TLM model; so RTL software development platform is unrealistic.
In fact, SystemC uses far more than that, roughly summarized under the following use of SystemC:
- Hardware architecture exploration, build algorithms, performance model;
- Verification engineer as the reference model (DPI through interface calls);
- Design engineers as design spec, design RTL;
- As a software engineer hardware model of software development;
- Make it possible to test a variety of advance;
总结：SystemC模型在芯片前端流程中重用度非常高，几乎可以作为各个部门（架构组，算法组，设计组，验证组，软件组）之间的桥梁，使得部门之间的沟通合作更加有效，大大增加工作效率。
几种使用SystemC模型的灵活测试案例：
- 验证人员可以提前搭建测试平台（使用SystemC model做DUT）；
在RTL可用之前，将SystemC model封装于System Verilog内，然后作为DUT搭建测试平台，并编写test cases。现在，如VCS等仿真软件已经内置了对SystemC的支持，无需使用DPI接口，就能将SystemC模型封装成System Verilog module。
- 混合仿真
按照上述方法搭建测试平台后，随着一个个模块或IP的RTL设计完成，逐渐用它们替换测试平台中相应的SystemC模型，然后运行测试用例，即可测试真实的RTL。
- 在FPGA平台上使用
虽然SystemC模型仿真速度要比RTL仿真快100x-1000x，但是依然没有FPGA速度快；因此在FPGA平台稳定之后，在FPGA平台上继续开发软件会更加高效。不过FPGA平台昂贵，面积有限，想将整个SOC放进FPGA是不可能的，但是驱动开发往往需要整个SOC的平台，这时可以将SOC的SystemC模型中自己关注的IP模型替换成FPGA实现，其他部分依然使用SystemC模型。
SystemC的优势
芯片设计前端的流程很长，和芯片前端相关的语言也很多，比如Verilog、VHDL、System Verilog、SystemC、Matlab、C/C++等等，但没有一个语言能够做到适合于整个前端流程，包括本文所说的SystemC也不行；每种语言都有适合使用的领域，只有在整个前端流程的不同节点上选择最合适的语言工具，并加以整合，才能加速产品开发。
注：本图引用自《SystemC: From the Groud Up》
如上图所示，它显示了各种语言工具适合使用的场所，其中：
- Verilog、VHDL主要用于RTL建模，并用来综合生成数字电路；
- System Verilog吸收了Verilog，既能够用于RTL建模，也能用于功能验证，基于System Verilog开发的UVM更是现如今最流行的验证方法学。
- Verie和e语言主要用于对ASIC进行功能验证；
- SystemC则主要用于架构级建模、软硬件建模、行为级建模；
- Matlab则主要用于算法设计、架构设计等。
我们熟知的Verilog/VHDL/System Verilog是最常见的硬件建模语言（更准确的说是硬件描述语言，即HDL），但是众所周知，HDL的开发难度大、故障率高、运行速度慢、与软件语言兼容性差，HDL用于开发RTL非常合适，但是用于抽象程度更高的建模就显得难堪大任。
C++属于高级语言，开发速度快、运行效率高（仅次于C）。考虑到几乎所有的底层软件都是用C/C++开发的，使用C++进行硬件建模，使得软硬件可以在同一种语言开发，从而让软硬件协同仿真更加方便高效。
SystemC library
下图是SystemC的框架图； SystemC的底层是C++及其标准库，当然也可包括其他的C++库，如boost库。
SystemC library包含多种功能，最核心的有如下几项：
- SystemC内核
SystemC内核用于调度SystemC process，其功能和Verilog和VHDL仿真内核非常相似；如果你不了解Verilog仿真内核，也可以认为它和Linux内核相似，只不过比Linux内核简单地多。
- SystemC process
SystemC process是由用户定义的，用来模拟硬件和软件的行为。Process是并行运行的，由SystemC内核调度执行。
- SystemC event
和Verilog仿真内核一样，SystemC内核是事件驱动型内核，所以理解event非常重要；SystemC event是指在特定时间点发生的事件。
- SystemC module
SystemC module用于将建模对象模块化、层次化；
- SystemC channel/interface/port/export
SystemC channel/interface/port/export用于实现模块间的通信；
SystemC中文教程安排
我们将分成6个部分来讨论SystemC，每个部分又包含2-6个课程。
第一部分 SystemC简介
第二部分 SystemC Object和Module
第三部分 SystemC process
第四部分 SystemC通信
第五部分 SystemC其他
第六部分 TLM2.0简介