Sequential Circuits
We took a look at the following questions sequential circuit:
1. Why use CPU timing circuits, sequential circuits with ordinary logic circuit What is the difference.
2. Trigger, what role latch circuit and a clock pulse timing is how they work.
With these two issues, we look at the logic circuit from scratch. To understand the logic circuit, first we have to understand the basic units of the logic circuit: a logic gate.
Logic gate
Logic gate is a basic unit of a digital circuit, which outputs the input bit values thereof are Boolean function. The most common logic gate is our well-known and, or, not.
With respect to the door, only a, b 1 are input, the output to 1.
For OR gate input a, b as long as there is a 1, then the output is 1.
For non-gate, if the input is an output of 0, 0 is input to an output.
These three are the most basic logic gates, we can achieve complex logical deduction by a combination thereof, such as the simplest and OR, XOR and so on. More complex logic, it can be achieved by a specific combination of basic logic, as we rely on application-level engineers with limited syntax can create virtually unlimited application of the same.
, In a very short period of time, corresponding changes in the output of the logic gate will always active, once a change in the gate input.
Use a lot of logic gates constructed a network, it has been a complex logic calculation block implementation (computational Block), referred to the combining circuit. Combinational circuits constituting the following principles:
1. The input of each logic gate to be connected to a system input, output, or the output of a logic gate of a memory cell (one of three).
2. The output of two or more logic gates can not be connected together, or may have conflicting signal or the circuit fault that caused the error.
3. The network must be acyclic, that can not have loops or network computing logic would be ambiguous.
Understand the basic concepts of logic gates and combinational circuits, we'll explain how to control the signal circuit is achieved.
control signal
We have said that more complex logic can also rely on a combination of basic logic, control logic inputs and outputs is no exception. In order to better understand how the control signal is a work, we introduce a useful combining circuit: bit multiplexer.
Wherein the control input s of the two AND gates. Wherein the logic gate is located above the! S && b, located below the gate is the logical AND s && a.
That is, when the inputted s is 1, b is unable to reach the input of the OR gate, 0 && b is always zero. In this case the input is the output of a whole circuit.
Conversely when the s input is 0, a can not reach the input of the OR gate, 0 && a constant zero. In this case the input is the output b of the entire circuit.
S can be seen that the potential level of the input directly determine a, b in which the input, which is a typical example of a control signal operating.
See how the control signal works, let's look at a simple hypothetical register is dependent on how the work of a clock control signal. A clock signal cycle from low to high and then from high to low.
, The register every single bit of the input signal to the signal as a control signal with the logical register and then into a register, it is conceivable that the low-level portion of the clock cycle, the signal can not be written to any register, wait the clock signal goes high only when the register becomes writable state. This is a simple flip-flop, the clock signal with the cycle of changing their status.
Of course, true that trigger more complex than just here to facilitate understanding cite the simplest example.
Understand these basic concepts, we look at the difference between ordinary combinatorial logic circuits and sequential circuits.
A combinational logic circuit with a difference between ordinary timing circuit
1. glitch tolerance
Essentially a combinational logic circuit, does not store any information. They are simply in response to an input signal, generating a coincidence output result of the expression of the logic input.
And a clock circuit with its own state, a state on a state of the timing circuit in addition to a current dependent on the input, but also on the circuit.
And we want to have their own state and the circuit can be calculated based on this state, the clock signal must be introduced periodically changing the storage device and controls the storage devices in the combinational logic circuit.
Storage devices are introduced readily understood, of course, no storage circuit is not their own state, because it does not store state information of the carrier, the carrier is stored in the memory circuit state information.
The role of the clock cycle is relatively not so easy to understand, we give an example to understand the role of clock signals:
We do not consider a combinational logic circuit, a clock signal:
As we have said, the logic gate is always active, once a logic gate input changes, the output will change in a very short period of time.
However, note that this "very short" description. Because of the different components of the quality / type, physical limitations of other routes of different lengths, different input to the output time is different.
FIG example, c is input to the gate and reach the bottom of the route to the two lines of the door, reaches the bottom of the door above the more of a NAND gate. C then the signal reaches the top of the door and natural than to reach the speed of the door faster below.
So when c signal is changed, there is a period of time, terminal F output is wrong, since the A && C has reached the terminal F, but B &&! C has not been reached, i.e. F1 than F0 arrive slow, there is a delay, the following Figure:
We call this situation as a "glitch."
Although the time glitch is very short, but the output is a circuit system is fatal. If we write memory error output glitch occurred during the time of the next logic is the same mistake again and let us scratching their heads.
The timing circuit does not occur while the above-described problems, we A / B / C is inputted to the F output as a complete operation, in one clock cycle. Then, A / B / C input to the clock edge trigger, F will result in the capture clock edge. And when the result of the acquisition, has crossed the output F of the burr in a stable state. Of course, such a high level within the duration of a clock cycle must be sufficient to reach a steady state output F.
Thus, the next action (occurring next clock cycle) if the output F based on the correct result. This is one difference between a timing circuit and a logic circuit common: tolerance of burrs.
It can be seen by a clock cycle, a change in the combinational logic circuit can be regarded as an input of a motion. In one clock cycle, to complete a basic circuit operation, the operation to ensure that the next cycle can obtain the correct clock circuit state.
If the sense circuit by action can not understand, we look at a very simple example:
int a=0; int b=a;
我们需要将 a=0 执行完后，执行 b=a 才有意义。a=0没有执行完成或未执行时，b=a 的执行完全没有意义。这就是程序按指令运转的重要性，正如电路按动作运转的重要性。
时钟周期将一个一个的动作隔离开来，确保每个动作在执行时，上一个动作已经完全执行完成了。而存储器则记录电路的状态，每个动作的执行结果放在存储器中供下个动作使用。
这正是CPU所需要的，CPU执行一条一条的指令正可以看作一个一个的动作（当然这里并不是指的一条指令，CPU的基本动作是比指令更加细化的单位，尤其是在流水线的引入之后。指令正是由一个个基本的动作构成的，这些基本动作指的是取指令/指令译码/指令执行/访存/写回/PC增加等等）。
时钟周期像人类的心跳，CPU随着时钟节拍快速又有条不紊的运行。正如前面所说，一个时钟周期必须足够CPU完全完成耗时最长的基本动作，时钟周期对于不同的CPU来说并不是固定的，确定一个CPU的时钟周期也是一个非常复杂的任务。
2.支持反馈逻辑
如果我们要实现一个计数器，如果用非时序电路实现是这样的：
上述电路是完全无法使用的，电路的下一个输出依赖电路现在时刻的状态，除了上一节所述的毛刺现象会造成结果的不可预计外，电路本身的逻辑存在死循环。
要支持反馈逻辑，必须使用寄存器将结果暂存起来，由时钟沿控制数据的反馈更新。
说完了时序电路的特性，我们看看时序电路如何组成处理器。
时序电路构成处理器
我们可以看到，一个最基本的处理器是这样一个电路：
1. 可以完成逻辑的运算。
2. 电路需要有自己的状态。
3. 每一个输出除了基于输入和处理逻辑外，还需要基于当前电路的状态。
时序电路可以很好的满足上述特性。对于时序电路来说，时钟脉冲便是电路的心跳，而寄存器是协同整个电路按心跳节拍运转的动脉瓣。
大多数时候，寄存器处于一种稳定状态，产生的输出等于它的当前状态。信号沿着寄存器前面的组合电路传播。这时产生一个新的寄存器输入，但当当前时钟脉冲处于低电位时，寄存器的输出仍保持不变。直到时钟脉冲变为高电位，输入信号便写入到寄存器中，成为下一个状态。直到下一个时钟上升沿，寄存器的状态和输出都不会发生改变。
电信号畅通无阻的在组合电路中传播，而寄存器就成为这种传播的屏障。只有在每个时钟的上升沿时，信号才可以通过寄存器进入下一个组合电路。
而一个个的组合电路执行着不同的动作，对于整个电路而言，时钟脉冲与寄存器的配合使得电路在每个动作执行完成后才会执行下一个动作。处理器在一个时钟周期内，执行完一个动作并把状态更新到寄存器。直到下一个时钟周期再执行下一个动作，此时上个动作已经完全执行完成了，而电路的最新状态也已经通过寄存器传播到了负责当前动作的电路中来。
上面便是一个最简单的处理器结构，左边标识了每部分电路对应的动作。
我们可以使一个时钟周期内执行完成整个指令执行（上述所有动作），这样下一个时钟周期执行下一条指令时可以保证上条指令可以执行完成。虽然这样时钟周期会长到让人难以接受，但它保证了指令流的正常流转。
或者我们可以将负责各个动作的电路间用寄存器隔离开来，一个时钟周期内只执行一个动作而不是一条指令，这样可以大大加快电路的整体效率。事实上流水线便是这样做的，为了更高的效率，许多流水线的层级非常深，一个取指/译码/执行三个动作可能被拆分成十五个甚至更多个动作。这样一个时钟周期内，就可以处理多条指令（当然它们处于不同的动作阶段）。
指令如流水一样进入处理器，而不是一条指令执行完成后下一条指令才进入处理器。虽然将指令的执行拆分成多个小动作会带来许多麻烦，比如流水线冒险，但其带来的收益是值得我们花费精力来解决这些麻烦的。
一个最基本的处理器的实现需要组合逻辑电路和两种存储设备：时钟寄存器（程序计数器和指令状态寄存器）和随机访问存储器（指令内存/数据内存和寄存器文件）。
组合逻辑不需要任何时序或控制，只要输入变化了，值就通过逻辑门网络传播。
那么我们还有四个硬件需要用时序控制：程序计数器/指令状态寄存器/数据内存和寄存器文件。因为时序控制的都是写入操作，而指令内存不需要写入操作，所以也不需要时序控制。
时钟脉冲控制着上述四个元器件的写入操作。时钟信号触发将值写入到指令状态寄存器和随机访问存储器。
处理器真的是一个非常宏大的话题，笔者能力极其有限，只能尽量的从非常宏观的角度上描述一下对处理器的认识（依然很吃力），如果有疑问欢迎评论区讨论。