Each filter controller STM32CAN group consisting of two 32-bit registers composition.
The required bit width different, each may be configured to filter 16 or 32 bit mode (as shown below, when FSCx = 1 for the 32-bit mode, FSCx = 0 when 16-bit mode). Meanwhile, the filter may be configured to model the masking mode and display mode (FBMx = 0 for the mask pattern, FBMx = 1 mode as a list).
Mask mode : choose for every message ID must be the same and whatever it.
List mode : given only the received ID, the other is not and will not receive.
Below these four cases are brief:
1, 1 32 Filter - mask pattern is
first written into a packet filter ID, the second filter, each bit corresponding to a predetermined inspection it is (set to 1), or whether it (set to 0).
For example, the first filter is set to 0x0000, this time if the second filter settings 0xFFFF, it means that all checks for each bit, that is, only to receive a packet ID of 0x0000. If the second filter settings 0xFFFE, whether it is to last, this time 0x0001 and 0x0000 can be to receive it.
Filter 32 2, 2 - List
of writing a packet filter ID, the second write standard message ID. At this time, only the ID of the received packet maybe.
For example, a first filter disposed 0x0000, the second filter settings 0x0001. At this point you can only receive ID packets 0x0000 and 0x0001 of the.
3, a filter 16 - mask pattern
and the second case is similar except that the bit width is reduced to 16 bits, only supports standard format ID, but the ID number can be screened for increased to two.
4, four 16-bit filter - the list mode
split into four 16-bit write enable filter 4 standard ID, receives only packets of four ID.