0. Introduction
SV introduced OPP, there will be similar to C ++ in the override and overload consideration.
1. override rewrite
Rewriting rewriting data members and methods have to rewrite See the following example
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Seen from the above, the parent class data members point to the handle is a member of the parent class.
If you want to call a member function handle subclasses overridden by the parent, then you need to function in the parent class defined as virtual types.
2. overloaded overload
In the SV does not seem to support the heavy load (overload), is not directly supported by the same method type, different parameters.
In the following example, SV B to check the function of the A dis dis function returns the different types of error.
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3. override conditions
Subclass want to correctly override the parent class virtual function, it is necessary to ensure that the following four points:
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Functions can be overloaded functions.
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The same function name
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Return of the same type
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The same parameter list
Subclasses to correctly reload the parent class virtual task, the need to ensure the following three points:
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Tasks can be overloaded task.
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The same task name.
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The same parameter list.
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4. new override it may be
Before the interview asked about the new function can override it?
UVM mentioned in the top UG1.1 P62 page "there are limitations on overriding new () in object-oriented language such as System Verilog." This seems to explain the new can be overloaded, but there are some limitations.
In the fifth chapter "UVMPrimer" in the mentioned, new () function it can be overloaded. such as:
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