SV——generate constructs

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0. Introduction

    construct is used to generate one or more embodiments of the generate block; generate block may be a module item, or a sequence of statements nested generate block. But you can not have a port statement.

   generate scheduling is in elaboration stage, rather than in simulation. The results generate scheme before simulation to determine . All expressions generate scheme stage should be a constant expression.

   ...... endgenerate can use keywords generate, of course, can not.

   generate constructs有两种loop generate constructs 和conditional generate constructs。

 

1. loop generate constructs

In cycle generation, generate a generate block is repeated a plurality of times. Loop index variables should be declared as genvar .

The genvar is used as an integer during elaboration to evaluate the generate loop and create instances of the generate block, but it does not exist at simulation time. A genvar shall not be referenced anywhere other than in a loop generate scheme.

note:

  1. Generating nested loops, different variable name can not generate the same genvar.

  2. If you generate block is named, the name can not be keywords, other variable names coincide, it is best not to coincide with other block name.

// A parameterized gray-code–to–binary-code converter module using a loop to generate continuous assignments
module gray2bin1 (bin, gray);
parameter SIZE = 8; // this module is parameterizable
output [SIZE-1:0] bin;
input [SIZE-1:0] gray;
genvar i;
generate
for (i=0; i<SIZE; i=i+1) begin:bitnum
    assign bin[i] = ^gray[SIZE-1:i];
    // i refers to the implicitly defined localparam whose
    // value in each instance of the generate block is
    // the value of the genvar when it was elaborated.
end
endgenerate
endmodule
module addergen1 (co, sum, a, b, ci);
parameter SIZE = 4;
output [SIZE-1:0] sum;
output co;
input [SIZE-1:0] a, b;
input ci;
wire [SIZE :0] c;
genvar i;
assign c[0] = ci;
for(i=0; i<SIZE; i=i+1) begin:bitnum
    wire t1, t2, t3;
    xor g1 ( t1, a[i], b[i]);
    xor g2 ( sum[i], t1, c[i]);
    and g3 ( t2, a[i], b[i]);
    and g4 ( t3, t1, c[i]);
    or g5 ( c[i+1], t2, t3);
end
assign co = c[SIZE];
endmodule

 

2. conditional generate constructs

The conditional generate constructs, if-generate and case-generate, select at most one generate block from a set of alternative generate blocks based on constant expressions evaluated during elaboration.

 

Can if - performs condition judgment else, case.

// 通过if--else判断
module multiplier(a,b,product);
parameter a_width = 8, b_width = 8;
localparam product_width = a_width+b_width;
// cannot be modified directly with the defparam
// statement or the module instance statement #
input [a_width-1:0] a;
input [b_width-1:0] b;
output [product_width-1:0] product;
generate
    if((a_width < 8) || (b_width < 8)) begin: mult
    CLA_multiplier #(a_width,b_width) u1(a, b, product);
    // instantiate a CLA multiplier
    end
    else begin: mult
    WALLACE_multiplier #(a_width,b_width) u1(a, b, product);
    // instantiate a Wallace-tree multiplier
    end
endgenerate
// The hierarchical instance name is mult.u1
endmodule


// 通过case判断
generate
    case (WIDTH)
        1: begin: adder // 1-bit adder implementation
            adder_1bit x1(co, sum, a, b, ci);
        end
        2: begin: adder // 2-bit adder implementation
            adder_2bit x1(co, sum, a, b, ci);
        end
        default:
            begin: adder // others - carry look-ahead adder
            adder_cla #(WIDTH) x1(co, sum, a, b, ci);
        end
    endcase
// The hierarchical instance name is adder.x1
endgenerate

 

 

 

 

 

 

 

 

 

 

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