2018-2019-1 20175314 "Information Security System Design Basics" Week 4 learning summary

2018-2019-1 20175314 "Information Security System Design Basics" Week 4 learning summary

Learning content summary

• ISA: instruction processor supports a byte-level coded instructions and called its instruction set architecture. Different processors have different ISA.
• Adventure: an instruction or operand locations are still dependent on other instructions in the pipeline.
• Y86-64 programs register 15, which is% rsp push, pop, call and return instructions seat stack pointer, flag ZF, SF, OF holds the most recent arithmetic or logical instructions related information caused by influence.
• Y84-64 comprising only an 8-byte integer operations. Byte-level coded instructions required ranging from 1 to 10 bytes, the first byte of each instruction type instruction indicates that this is the access code portion of the upper four bits, the lower 4 bits is a functional moiety.
• Some basic instructions Y84-64 see textbook P246, like IA32, coding method which employs small pieces.
• An important property of a set of instructions that must have a unique byte code interpretation.
• Stat programmer visible status: ①AOK, normal operation; ②HLT, organic halt instruction encountered; ③ADR, encountered illegal addresses; ④INS: illegal instruction. When an exception is encountered, stop the program or to call a signal handler user-defined.
• pushq instructions will stack pointer by 8, and tells a register value is written in the memory. But when performing pushq% rsp instruction, the processor behavior is uncertain, because the stack register will be modified in the same command.
• The combination of a lot of logic gates into a network: ① outputs of two or more logic gates not connected together; ② the network must be acyclic; ③ input of each logic gate input system must be connected to a memory cell or a the output, or the output of a logic gate.
• Combining circuit is essentially does not store any information. In order to generate the timing circuit must be introduced into the apparatus information storage bit. Storage devices are controlled by the same clock.
• All calculations Y6-64 achieve the required instruction can be organized into six basic stages: fetch, decode, execute, access, write back, updates PC.
• SEQ comprising a combination of logic and implementation of the two memory devices: random access memory and clock registers.
• Processor follow the principle of "never read back", and never needed to complete execution of an instruction to read and updated by the command state to address the situation similar pushq% rsq cause "ambiguity" of.
• By performing the steps required by each different instructions organized into a unified process, can be used small amounts of various hardware units, and a clock to control the order of evaluation, in order to achieve the entire processor. SEQ problem is too slow, so the clock must be very slow to make a signal to propagate all cut in one cycle.
• In naming system, capitalized prefix refers to a pipeline register, lowercase prefix refers to a pipeline stage.
• I guess branch direction guess based on the start and fetch technique called branch prediction. All processors have adopted some form of such technologies.
• Pipeline hazards can be divided into two categories: data hazards and control risks, first consider the former consider the latter.

Code debugging and problem solving in the process

• Problem: After using 32-bit code will run more warning and can not continue
  
• Workaround: Update jdb fix bug:

wget http://ftp.gnu.org/gnu/gdb/gdb-8.3.tar.xz
 tar -xf gdb-8.3.tar.xz
 cd gdb-8.3/
 ./configure
 make
 sudo cp gdb/gdb /usr/local/bin/gdb

Code hosting

Feelings experience

More classroom test this week, but as long as fully prepared before class, or you can guarantee quality and quantity, although the first test because of a computer problem two minutes late submission, but later tests are successfully completed, reflect efforts will have visible results.

Learning progress bar

	The number of lines of code (add / accumulate)	Blog amount (add / accumulate)	Learning time (add / accumulate)	Important growth
aims	5000 rows	30	400 hours
the first week	200/200	1/1	20/20
the second week	300/500	1/1	10/15
The third week	200/500	1/1	10/12
the fourth week	500/500	1/1	12/12

• Plan study time: 12 hours

• The actual study time: 12 hours

Reference material

• "In-depth understanding of computer systems V3" Study Guide