No.5 gate-level modeling

VerilogHDL primitive gate built:
a multiple-input gate: and, nand, or, nor , xor, xnor;
multiple output gates: buf, not
tri-state gate: bufif0, bufif1, notif0, notif1 ;
pull-up, pull-down door: for doing pullup, pulldown;
the MOS switch: cmos, nmos, pmos, rcmos , rnmos, rpmmos;
bidirectional switch: tran, tranif0, tranif1, rtran , rtranif0, rtranif1;

Example 1: 2-4 decoder

module dec24(a,b,en,dataout);
input a, b, en;
output [0:3]dataout;
wire abar, bbar;

not #(1,2)
u0(abar, a);
u1(bbar, b);
nand #(4,3)
s0(dataout[0],en,abar,bbar),
s1(dataout[1],en,abar,b),
s2(dataout[2],en,a,bbar),
s3(dataout[3],en,a,b);
endmodule

Example 2: master-slave flip

module d_flipflop(d, clk, q, qbar);
input d, clk;
output q, qbar;

not
n0(not_d, d),
n1(not_clk, clk),
n3(not_y, y);
nand
x1(d1,d,clk),
x2(d2,clk,not_d),
x3(y,d1,ybar),
x4(ybar,y,d2),
x5(y1,y,not_clk),
x6(y2,not_y,not_clk),
x7(q,qbar,y1),
x8(qbar,y2,q);
endmodule