Gem5 is a modular discrete event driven full-system simulator, which combines M5 and GEMS in the best part, M5 provides a highly configurable simulation framework, support for multiple ISAs and CPU model; GEMS complements the M5 characteristics, a detailed and flexible memory system, comprising a plurality of cache coherence protocol and interconnect models, is a highly configurable, the ISA integration of multiple, multiple CPU architecture simulator model.
gem5 simulator currently supports multiple ISAs, including Alpha, ARM, MIPS, Power, SPARC and x86. Simulator allows modularity ISAs inserted into these different models and general purpose CPU system memory, without the need for each CPU ISAs provided a proprietary model and model store, this makes a higher degree of modularity and easy simulator switch between different CPU.
M5 was developed by the University of Michigan in an open source multiprocessor simulator, has been widespread concern in the industry, a lot of high-level papers M5 are used as a research tool. On the other hand, Wisconsin launched GEMS enables detailed and flexible simulation of the storage hierarchy, including support for a variety of different cache coherence protocol and interconnect models. The current GEM5 is a tightly coupled version of the M5 and GEMS.
1. The overall objective
Gem5 target simulator is to become an excellent tool for structural modeling systems. Three key aspects of this goal is the flexibility, availability, highly collaborative.
1.1 Flexibility
Flexibility is the foundation of a good simulator. When landing an idea from concept to a particular design, programmers need a tool to evaluate the system, balance simulation speed and accuracy. Different types of simulation experiments may have different requirements. For example, certain experiments may require a sophisticated CPU model, but not necessarily multi-core model. And some experiments may require multiple CPU, but the CPU does not need too many details. So flexibility is essential simulator, programmers can accomplish more with less overhead work faster.
gem5 simulator is a tool, a variety of functions and components, covering the tradeoff between speed and accuracy of the simulation. As shown in Figure 1.
CPU model
gem5 simulator currently offers four different CPU models: AtomicSimple, TimingSimple, InOrder and O3. And non-pipelined CPU AtomicSimple TimingSimple model AtomicSimple the IPC is a smallest single CPU model for fast simulation function; TimingSimple Similarly, memory access but uses a timing model for the memory access latency statistics; the InOrder is a sequential CPU pipeline model, in this mode, can be configured to support a number of hardware threads; O3 is a chaotic sequence pipelined CPU model, and supports superscalar SMT. InOrder and O3 are the execute-in-execute (command execution in the execution stage only) design.
System Mode
gem5 supports two execution modes: System-call Emulation (SE), and Full-System (FS).
SE mode, when the program executes a system call, gem5 will be captured, while analog calls, usually passed to the host operating system. By simulating the most system calls, avoiding the need for peripherals and OS modeling. SE mode, no thread scheduler, the thread must be statically mapped to the cores, thus limiting the multi-threaded applications. SPEC CPU benchmark typically run in SE mode. FS (system-wide) mode a complete system, including the OS and peripherals, modeled, and the kernel can perform user instructions. FS mode, gem5 provide a suitable environment to run a bare-metal operating system, include interrupts, exceptions, etc., not all ISAs support this mode. FS with respect to the SE, higher accuracy can be performed more types of loads. Although the SPEC CPU benchmark tests are usually run in SE mode, but running in the FS mode, they will provide a more realistic interaction with the OS. Many OS services or requiring I / O workload equipment may only run in FS mode.
Storage System
Storage system supports two models: Classic and Ruby. Classic model (from M5) provides a fast and easy configuration of the memory system; the Ruby Model (from GEMS) provides a flexible and can accurately simulate the system memory, cache coherence support. Ruby support large memory model interconnection topologies, including both two different network models. The link between the component uses a simple statement of the python file, and then create routing via the shortest path analysis. After determining the link and routing tables, be implemented according to different network models. Two networks model:
1, Simple Network model: only the link, link bandwidth and latency route, and there is no control on the router model resource contention and traffic.
2, Garnet network model: to establish a detailed routing model, comprising the resources to compete and flow control.
1.2 Availability
gem5 user There are several types, each person has different goals and needs. These include academic and corporate researchers, industrial engineers, undergraduate and graduate students. Gem5 developers hope gem5 simulator can be widely available to all of these types of users. gem5 License (based on BSD) is friendly to business users and academia. gem5 community is very active, there is a lot of collaboration technologies can promote the use and development of gem5.
2. Design Features
This section focuses on several key aspects of the implementation gem5: object-oriented design, Python integration, the use of standardized interfaces and languages in specific areas.
2.1 Object-Oriented
Flexibility is an important goal gem5 simulator, as well as key aspects of its success. The flexibility of object-oriented design is achieved. Each major component gem5 simulation simulator is SimObjects, they share configuration, initialization, statistics and serialization (checkpoint) of public behavior. SimObjects includes specific hardware components (e.g., processor cores, cache, and peripheral interconnecting elements) as well as more abstract entities (processes of simulation for system calls and context associated workload). Here peripherals include simple timer to complex network interface controller, by using a common base class to encapsulate the device interface, the code in order to avoid repetition, to simplify the implementation. All SimObject by two types of objects represented, python and c ++ class class. Python class definitions specified SimObject parameters and configuration may be used in the script file. Python is a common base class instantiation, named set parameter values and provides a uniform mechanism. C ++ class contains SimObject state and other acts, includes both the key performance simulation model.
2.2 Python Integration
gem5 85% of code written in C ++, 15% SimObject Python code responsible for initialization, configuration and analog control. Simulator at startup immediately starts executing Python code, the main function uses standard python written all command-line processing and activation code are python code.
2.3 Domain-Specific Languages
Providing two specific language gem5 art, for a description of ISA (inherited from M5), another cache coherence protocol described for (Inherited from GEMS).
ISA DSL
A uniform binary instruction decoding and their semantics specification. gem5 instructions described by using a common base class in C ++ in order to achieve independence of the ISA. Each ISA re base class inherited methods, for example, execute (). ISA concise description language allows the user to specify the desired c ++ to code.
Cache Coherence DSL
SLICC is a DSL, for flexible implementation cache coherence protocol. SLICC currently supports broadcast-based coherency protocol AMD Opteron and CMP directory protocol. SLICC the cache, mem, DMA controller defined as a separate per-memory-block state machine, a combination of these state machines is called the entire protocol. The SLICC gem5 the protocol defines a set of states, events, and conversion operation while the components are bound together (e.g., cache) independent of state machine logic and protocol specific. The automatically generated gem5 SLICC python and c ++ files also support local variable, to simplify programming improve performance
2.4 standardized interface
Standardized interface is object-oriented foundation. There are two core interface port (Port) interface and a message buffer (message buffer) interfaces.
1, ports: a memory connected to the object, and comprising a cpu caches, caches to the bus, the peripheral bus and memory. The interface supports three mechanisms to access the data, 1) timing mode, memory accesses to model with detailed timing, a message of request and response mechanisms; 2) atomic model for acquiring timing information, but no messages mechanism, the state will change directly; 3) functional mode, the operation does not change the stored timing information.
2, the interface message buffer: Ruby port interface used to connect peripherals cpu and, at the same time using the internal message buffer interface Ruby objects. Both interfaces are very similar.
3. User Resources
All gem5 simulator documents and information are available on the website http://www.gem5.org found on. The site includes how to check, to build and run gem5 explanation simulator, and how to download OS binary files and disk images and other files for added support.
Original: Big Box Gem5 Profile