In the first few days of ARM interview, asked about the bus architecture, the main thing is that set AMBA. For AMBA before the class learned a little, but very superficial. Internet search a bit for the interview, also saw part of the agreement to add a little, but less contact, understanding is not deep, things did not come across before asked, was stumped. I asked my slave HREADY What are the two signals, each with what, after HREADY reset is high or low.
There are two HREADY the slave input signal and output HREADY HREADY.
Output HREADY
HREADY output is better understood, it indicates whether the slave is currently ready to accept or send data, if it is high (AHB protocol recommended high to indicate readiness) represents the slave is ready, not ready for the low representation.
Enter HREADY
When the slave is not ready for data transmission, such as the following data write operation:
In the data phase, master to the slave HREADY sampled low, the current data phase needs to be delayed to the next cycle.
However, if there are two slave data to be transmitted, after the transfer is completed slave1 slave2 take the bus. slave1 when writing the final data is not ready, HREADY output is low, then the master will be in the next cycle (slave1 second data cycle) did not just continue to write past data on the bus, for slave1 sampling. However, in the next cycle (Slave1 second data cycle) it was supposed to be transmitted with slave2, and assuming that the HREADY slave2 is high, this case is considered to be slave2 with their data transmissions.
But the master will pass the data on the bus slave2 the altar slave2 sampling in the next cycle again, but this time found slave2 read and write address and the last one was the same, protocol error problem occurs.
So slave2 need to know the last time slave1 HREADY sampling data transmission will be high. The general approach is to output all of the slave do HREADY and (AND) operation, after all HREADY as input the output of the slave.
In this case, slave2 in its data cycle to know on a cycle, that is, the data cycle slave1 successful transmission of the data.
In this case, will know after power-on reset, slave output HREADY high, to prevent deadlock.
reference:
https://blog.csdn.net/fanyongwinner/article/details/51890908