source:
In the last Chinese journals to see.
1. AHB Arbiter signals:
2. The arbitration process involves four basic steps:
1. Use HBuSREQx master access to the bus request signal;
2. Arbiter setting the appropriate HGRATx signal indicative of application of the master is successful, it will get access to the bus when the current transmission is completed;
3. The master device has an address / control bus;
4. The master device has a data bus.
3. Request bus access
1. Use HBUSREQx master wants control of the bus arbiter request, arbiter HBUSREQx sampling edge of the clock signal, then arbitration algorithm (not specified in the protocol) to decide which bus master takes over.
2. If the lock request bus master (not want to interrupt requests from other transmission is the master), the master must also asserted HLOCKx signal, so that the host can not control the other bus.
3. Application to a bus master burst transfer may be performed once, and Arbiter needs to know HTRANS HBURST signal to knew a burst stops. If you want to master but also for burst transfer after a burst, then the master will need to request HBUSREQ again in the burst transmission.
4. If the host are lost in a burst control of the bus, then the need to reapply HBUSREQ.
5. If the master undetermined length for burst, then the master has been required to apply HBUSREQ during transmission.
6. If there is no master requests bus, then the bus will be handed over to the default host, send IDLE on HTRANS.
4. The master bus arbiter does not respond to the request:
arbiter arbitration algorithm can be initiated by the master HBUSREQ arbitration, which decided to take the bus master, but in the following cases, currently occupied by the bus master to maintain occupancy of the bus:
1. HLOCK signal lock with the current master bus.
2. The current master burst transfer in a steady.
3. occurs corresponding to the request of the master device is shielded split.
5. Grant bus
arbiter indicates the highest priority bus master by which HGRANT signal, and the current HREADY is high (i.e., the current data write is completed) will be granted to the highest priority bus master time. At the same time changing the arbiter to indicate which master HMASTER occupied bus.
6. burst early termination
Arbitration does not usually handed over before the end of the burst bus to the new host. However, if the arbitrator decides burst must be terminated early in order to prevent the bus access time is too long, it may be transferred to another bus access to the host before the completion of a burst. If the host loses access to the bus burst transfer, it must re-assert bus request signal. The host must ensure HBURsI 'and coral limit ANS signals are updated to ensure that no longer perform a complete burst transmission.
7. arbitration algorithm
Arbitration algorithm has a fixed priority arbitration (Fixed priority), cyclic priority arbitration (Round Robin), or the randomness of Arbitration (Random) and competition arbitration priority (Tournament)
Fixed priority algorithm, refers to the priority of each bus master device is pre-determined, fixed in the arbiter in the arbitration process.
Priority algorithm and the cycle is different, priority of each master device during the arbitration of the arbiter is not static, but is changed in accordance with certain rules.
Both have advantages and disadvantages, fixed priority algorithm, can be given a higher priority for those important large-time data transmission, and data transmission or master devices frequently need to occupy the bus, in order to effectively utilize the AHB bus. Disadvantage of fixed priority algorithm that may arise bus master "Cheng Si" and "starving to death" phenomenon, that is a higher priority master is always better than a low-priority bus master gain access, leading to priority low-level device can not receive timely access to the bus caused by data transmission congestion.
In contrast, cyclic priority algorithm can overcome this "full hungry" unevenness drawbacks, the circular priority algorithm, due to dynamically changing priority with each bus cycle, the identity of each device on the bus equality equal access to bus occupation rights. So, in a certain sense, the priority of the cycle is the fairest method. Robin priority drawback is that when large quantities of real-time data processing certain devices can cause reduced efficiency.
8. Some scenes arbitration
8.1 Ordinary Arbitration
The desired master acquired the bus arbiter asserting a bus request signal to the arbitration, the arbiter via arbitration according to the arbitration logic, the bus response signal sent HGRANT. Master is sampled on the rising edge of the clock signal HGRANT, when sampled HGRANT effective, and at the same time HREADY is high, indicating that the bus master granted access and may begin transmitting.
8.2 master lock arbitration
If you get access to the bus master does not want to be interrupted during transmission , and want continuous non-interrupted transmission, then the master at the same time issuing a bus request signal (HBUSREQ) can issue bus latch signal HLOCK , soon HLOCK set high.
When the master gains bus access arbiter will send a corresponding response signal HMASTLOCK, so arbiter will not be released to the other bus master, until the master itself HLOCK cancel latch signal is set low, the arbiter will bus arbitration operation, the master can be performed so that other bus operation. Here we assume that burst priority fixed length of transmission are not interrupted.
8.3 SPLIT transmission
Arbitration can also hope to complete the arbitration bus slave SPLIT transmission. When the master arbiter observed claimed SPLIT response is received, the master priority will be shielded to, when bus access is shielded master, the bus master will not be able to get access , even if no other bus master access the same time. Meanwhile, Slave master signal to be recorded in order to inform future restoration priority arbiter of the master . This can be emitted from the HMASTER arbitrator [3: 0] signal Richard. If all the master have received SPLIT response signal, the arbiter bus access will be transferred to the dummy master (one kind only send master IDLE transmission).
When the response to the SPLIT slave processed transmission requirements, will be issued HSPLIT. [15: 0] signals to the master arbiter HSPLIT samples of each rising edge of the clock [15: 0], when it receives HSPLIT [15 : 0], the original will be masked master of bus priority re-opened, so the master priority will revert to the original state and have the opportunity to regain access to the bus.
8.4 RETRY transmission
When RETRY response signal issued by slave, the master priority arbiter does not change. But when there are higher priority bus master issuing a request signal, the bus will get access to a high-priority master, but if you get the original master RETRY response time is the master bus request of highest priority, the or continue to occupy the bus will be, and can not be released to other needy master.