EDITORIAL words
Before you think might look at a variety of waveforms are designed, more single, boring. So this section, will be able to bring you a new feeling, modern electronic technology, image processing technology can be described as rapid development, its unique visual experience to bring you always so pleasant. Here, everyone dreams wing brothers and knocked on the door to the world of images, let us obsessed, intoxicated.
What is VGA ?
VGA (Video Graphics Array, a video graphics array), is an analog signal using a computer IBM made in 1987 shows the standard. This standard has been for today's PC market has been very time. Even so, VGA is still a lot of manufacturers to jointly support a low standard PC before loading their own unique drivers, must support the VGA standard.
VGA support simultaneous displaying 16 colors or 256 gray shades at higher resolutions of 640X480, and can display 256 colors simultaneously at 320X240 resolution.
XGA (Extended Graphics Array, extended graphics array), was invented by IBM in 1990, XGA newer version true color XGA-2 to provide a resolution of 800 × 600 pixels or 65,536 kinds of colors to provide 1024 × 768 pixels resolution, image resolution levels may both individuals and small businesses today's most commonly used.
VGA Interface
The pin functions:
Development board circuit diagram is as follows:
As can be seen from the circuit diagram, our external VGA and no special chip, that is to say, the only thing we might want to focus on is its principle and the timing of the display, then the next we look at what specific scanning principle of VGA Yes.
8.7.4 VGA display principle
8.7.4.1 scan mode
VGA monitor scanning into progressive scan and interlaced scan: Progressive scan is the first point to start from the top left corner of the screen, from left to right by-point scanning, scanning every row, electron beam back to the left of the screen next line starting position, during which, CRT electron beam blanking, the end of each row, synchronized with the line synchronization signal; when all rows have been scanned, one frame is formed, a field sync handy synchronization signal, and a scan back to the upper left of the screen, at the same time the vertical blanking interval, the next frame starts. It refers to a line interlaced scan every line during electron beam scanning, a screen Saowan then return to the rest of the scan lines, interlaced display flashing quickly, the user may cause eye fatigue (progressive scanning this experiment the way).
After scanning principle is clear, we immediately look at VGA rows, columns synchronous timing
Timing ranks
Column synchronous timing
Line synchronization timing
VGA define row and column timing required timing synchronization pulse ( A section), the display direction ( B section), a timing section ( C section) and the leading edge of the display ( D segment) four parts. Industry standard VGA display mode requires: line synchronization, the synchronization column are negative, i.e. sync pulse is a negative pulse is required.
A VGA apparent line sequence: each line synchronization pulse has a negative polarity rows ( A section), the end flag data line, but also the start flag of the next line. After the sync pulse is displayed in the rear ( paragraph b), by the display timing paragraph (c para) as a bright display process, the RGB data driving each pixel on one row, thereby displaying a row. In the last line of the forefront of the display ( D segments). No image is projected onto the screen, but the blanking signal inserting than during the display period. Sync pulse along the leading edge and the display are displayed after the horizontal blanking interval when the blanking valid, the RGB signal is invalid, the screen does not display data.
Standard display
There are many standard VGA display, as follows:
In this experiment a standard display 800 * 600 * 60Hz Example. (800 is the number of columns, 600 is the number of rows, 60Hz refresh frequency of one screen)
Timing line: the number of lines corresponding to the screen is 628 (a + b + c + d = e above), where 600 (c para) of display lines; each line are line synchronization signal ( A segment) as a four line periods low level;
Column Timing: each display comprises a row 1056 (a + b + c + d = e above), where 800 (c para) of the effective display area, the column has a synchronization signal (a period) for each column, row 128 low cycle.
The effective area of the display screen as shown below :
Top frame
After the principle is clear, our mission is to design this VGA controller, drive LCD display shows all red. Now design system diagram as follows:
Description:
(1) the clock frequency dividing module (PLL)
We used the crystal development board is 50MHZ, because of our display standard is 800 * 600 * 60Hz, the system clock frequency of the desired display mode of 40MHz, so we divide by calling PLL implemented.
(2) VGA synchronization controlling module ranks (VGA)
VGA display standard is necessary to set the ranks of the synchronization signal, to calibrate the effective display region, which is the core of the VGA driver module
(3) VGA color display control module (R_g_b)
The effective display area, the color image output control r, g, b signals
Port Description top module
| Port Name |
Port Description |
| clk_sys |
50MHz system clock input |
| rst_n |
System Reset Low |
| vga_r |
Red primary color signal output VGA |
| vga_g |
Green primary color signal output VGA |
| vga_b |
Blue primary color signal output VGA |
| vga_hs |
VGA synchronizing signal output column |
| vga_vs |
VGA output line synchronizing signal |
Next we learn the specific code for each module to achieve, due to the frequency module we use the phase-locked loop, whereas the previous chapter, we used to have a special discussion of the phase-locked loop, so we will not repeat them here.
8.7.7 code implementation
VGA ranks of synchronization control module
| /**************************************************** * Engineer: Dream Brother Wing * QQ : 761664056 * The module function: VGA ranks of synchronization control module * *****************************************************/ 01 module vga( 02 INPUT CLK , // connected to the frequency-divided clock as 40MHz 03 the INPUT rst_n , // low reset 04 05 the Output REG vga_hs , // VGA column synchronization signal 06 the Output REG vga_vs , // VGA horizontal synchronization signal 07 Output EN // display enable signal region 08 ); 09 10 Parameter hy_all = 11'd1056 , // column timing Hy_a 11 = 11'd128 , 12 hy_b = 11'd88 , 13 hy_c = 11'd800 , 14 hy_d = 11'd40 , 15 16 vy_all = 11'd628, //行时序 17 vy_a = 11'd4, 18 vy_b = 11'd23, 19 vy_c = 11'd600, 20 vy_d = 11'd1; 21 22 //用计数器限定VGA显示相应区域 23 reg [10:0] cnt_h;//列计数器 24 reg [10:0] cnt_v;//行计数器 25 26 //-----------------------列计数----------------- 27 always@(posedge clk or negedge rst_n) 28 if(!rst_n) 29 cnt_h <= 11'd0;//列计数器复位 30 else if(cnt_h == (hy_all-1))//所有列扫描完毕 31 cnt_h <= 11'd0;//列计数器清零 32 else 33 cnt_h <= cnt_h + 1'b1;//列计数器累加 34 35 //-----------------------行计数-------------------- 36 always@(posedge clk or negedge rst_n)//在一列计数完之后将行加1 37 if(!rst_n) 38 cnt_v <= 11'd0;//行计数器复位 39 else if(cnt_v == (vy_all-1))//所有行扫描完毕 40 cnt_v <= 11'd0;//行计数器清零 41 else if(cnt_h ==(hy_all-1))//所有列扫描完毕 42 cnt_v <= cnt_v + 1'b1;//行计数器加一 43 44 //---------------------限定列同步信号--------------- 45 always@(posedge clk or negedge rst_n) 46 if(!rst_n) 47 vga_hs <= 1'b1; //复位时置列同步信号为高电平 48 else if(cnt_h ==0) //列开始扫描 49 vga_hs <= 1'b0; //置列同步信号为低电平 50 else if(cnt_h == hy_a) //保持hy_a个时钟周期 51 vga_hs <= 1'b1; //置列同步信号为高电平 52 53 //---------------限定行同步信号-------------------- 54 always@(posedge clk or negedge rst_n) 55 if(!rst_n) 56 vga_vs <= 1'b1; //复位时置行同步信号为高电平 57 else if(cnt_v ==0) //行开始扫描 58 vga_vs <= 1'b0; //置行同步信号为低电平 59 else if(cnt_v == vy_a)//保持vy_a个时钟周期 60 vga_vs <= 1'b1; //置行同步信号为高电平 61 62 //----------限定显示有效区域，设定使能信号---------- 63 wire [12:0] en1;//列有效标志 64 wire [12:0] en2;//行有效标志 65 //列有效区域 66 assign en1 = (cnt_h >= hy_a + hy_b && cnt_h <= 67 hy_a + hy_b + hy_c)?(cnt_h-hy_a-hy_b):11'd0; 68 //行有效区域 69 assign en2 = (cnt_v >= vy_a + vy_b && cnt_v <= 70 vy_a + vy_b + vy_c)?(cnt_v-vy_a-vy_b):11'd0; 71 assign en = (en1 > 0 && en2 > 0 )?1'b1:1'b0;//行、列共同有效区域800*600 72 73 endmodule |
代码说明：本模块是VGA行列同步控制模块，第10~20行定义了显示标准为800*600*60的一些参数，第26~42行写的是行列计数器，当计数满一行之后，行计数器清零，当所有列扫面完毕之后，列计数器清零；第45~60行是限定列显示和行显示的控制逻辑；第63~71行定义了2个有效区域，第66~67是列有效区域，69~70是行有效区域，第71行是当列有效区域和行有效区域都有效的区域。
VGA色彩输出控制器模块
| /**************************************************** * Engineer : 梦翼师兄 * QQ : 761664056
* The module function:VGA色彩输出控制器模块 * *****************************************************/ 01 module r_g_b( //颜色控制模块 02 //端口信号：模块的输入输出接口 03 input en, //使能信号 04 05 output [2:0] vga_r, //红色(3位：根据数值的变化，控制颜色的深浅） 06 output [2:0] vga_g, //绿色(3位：根据数值的变化，控制颜色的深浅） 07 output [1:0] vga_b //蓝色(2位：根据数值的变化，控制颜色的深浅） 08 ); 09 10 //-----------在使能区域显示相应的颜色---------- 11 assign vga_r = en?3'b111:3'b000;//在使能信号下输出红色 12 assign vga_g = 3'b000; //无绿色输出 13 assign vga_b = 2'b00; //无蓝色输出 14 15 endmodule |
第11行在输入en信号有效的情况下，输出全红基色信号，绿色和蓝色都不输出。
VGA显示顶层模块
| /**************************************************** * Engineer : 梦翼师兄 * QQ : 761664056 * The module function:VGA显示顶层模块 * *****************************************************/ 01 module top( //顶层模块：将各个模块组合 02 //外部接口 03 input clk, //系统时钟50MHz 04 input rst_n,//低电平复位 05 output vga_vs,//VGA行同步信号 06 output vga_hs,//VGA列同步信号 07 output [2:0] vga_r,//红色输出信号 08 output [2:0] vga_g,//绿色输出信号 09 output [1:0] vga_b //蓝色输出信号 10 ); 11 //内部信号：模块内部的接口信号，比如模块pll的输出信号c0， 12 //通过内部信号clk_40与模块vga的输入信号clk相连 13 wire clk_40; 14 wire en; 15 16 //模块例化 17 pll pll( //分频时钟，用锁相环产生， 18 .inclk0(clk), //在显示标准800*600*60HZ中，时钟指定为40MHz 19 .c0(clk_40) 20 ); 21 22 vga vga( //接入分频时钟，限定显示的有效区域 23 .clk(clk_40), 24 .rst_n(rst_n), 25 .vga_vs(vga_vs), 26 .vga_hs(vga_hs), 27 .en(en) 28 ); 29 30 r_g_b r_g_b( //在有效区域内，显示相应颜色 31 .en(en), 32 .vga_r(vga_r), 33 .vga_g(vga_g), 34 .vga_b(vga_b) 35 ); 36 37 endmodule |
综合编译以后，我们可以查看RTL视图，查看电路综合结果和预想是否一致，调用RTL视图如下：
由此可以看到电路综合出的结果和我们预先设计的框架相同。接下来我们编写测试代码，用来验证我们设计的正确性。
| /**************************************************** * Engineer : 梦翼师兄 * QQ : 761664056 * The module function:VGA显示测试模块 * *****************************************************/ 01 `timescale 1 ns/ 1 ps //设置仿真时间单位与精度分别为1ns/1ps 02 module test; 03 //端口信号定义，激励信号为reg型 04 reg clk; 05 reg rst_n; 06 wire [2:0] vga_r; 07 wire [2:0] vga_g; 08 wire [1:0] vga_b; 09 wire vga_hs; 10 wire vga_vs; 11 //初始化激励，以及给相应激励赋值 12 initial 13 begin 14 clk = 0; 15 rst_n = 0; //在复位阶段，将激励赋初值 16 #200.1 rst_n = 1; //在延时200ns后将复位信号置为1 17 end 18 always #10 clk = ~clk; //时钟为1/20ns = 50MHZ 19 //模块例化 20 top top( 21 .clk(clk), 22 .rst_n(rst_n), 23 .vga_hs(vga_hs), 24 .vga_vs(vga_vs), 25 .vga_r(vga_r), 26 .vga_g(vga_g), 27 .vga_b(vga_b) 28 ); 29 endmodule |
仿真分析
从波形可以看出，当en有效时，vga_r输出3’b111，说明设计是正确的。
将代码下载到开发板，可以看到整个屏幕全部显示红色，说明我们本次的设计是正确的。