= Dynamic power consumption CMOS transistor static power +
There are two expressions dynamic power, the difference of the two representations is that: the pipe the internal capacitor charge and discharge power consumption attributed who , in a first common theoretical expression, the second expression is common in power tools EDA calculation.
The first said:
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Dynamic power consumption + = short-circuit power switch
Switching power: means for pipe "associated capacitors' charging and discharging for power consumption in the tumbling process, where" dependent capacitance "includes pipe internal node capacitance and the load capacitance.
Short-circuit power: refers to a tube in the tumbling process, PMOS and NMOS are simultaneously turned on, VDD from the power supply to the short circuit path between the ground VSS power consumption.
The second said:
Dynamic power consumption = internal load power consumption +
Load power consumption: refers to the tube to "load capacitance" for power consumption in the charging and discharging process of reversal.
Internal Power: refers to a tube in the tumbling process, the internal node capacitance for power consumption and short circuit current consumption consumed by charging and discharging.
EDA tools dynamic power calculation, and calculates an internal load power consumption, respectively.
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Internal consumption: Methodological internal current as a function of input power analog output transition with a load (load capacitance), the internal power consumption of each tube will be defined in the foundry in the library, common two-dimensional table, index is ( input transition, output load cap), and occasionally there are three-dimensional table, index is (input transition, output load cap, second output load cap).
In the library will define the cell of rise_power and fall_power respectively. Typically, after the internal power 90nm will define the state of each input pin of each timing arc and each Cell, called: path dependencies internal power. Under certain circumstances libraries, each formula EDA tools should be big bad not bad, here's an example to the formula Genus:
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TR refers to the effective arc or on a pin toggle rate. Arcij effective toggle rate depends on the probability (Probability) which arc activated and a corresponding input pin of the toggle rate .
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Φ is the internal power value obtained from the look-up table in the library.
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Si is an activated transition occurs inverted output of the input pin.
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Cj is the output load capacitance pin.
Example: In Case 2 input AND gate, said fragment library defines an internal power Z pin A1 to the PIN, the transition is assumed that A1 18ps, Z is the load 0.336pf, A1 is the total rate of 0.5, probability is 1, because there is no library 18ps in the transition index, need to interpolate between 24ps and 12, the power consumption of the internal gate is:
toggle_rateA1 × probabilityA1 → Z × ΦA1 → Z(0.0018, 0.336)
=0.5 × rise_power(0.0018, 0.336 ) + 0.5 × fall_power(0.0018, 0.336 )
= 0.5 × 0.0061 + 0.5 × 0.0059
Load power: net load here includes all the cell-driven and all sink input pin capacitance cell, which is calculated as:
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CL is the load capacitance = sum (capacitances of the net, input pins driven by the net). Can be obtained by the corresponding value in the attribute pin_capacitance wire_capacitance genus and Lane.
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V is the operating voltage.
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TR 是toggle rate.