Reprinted from the article: http://www.pythonheidong.com/blog/article/2868/
A complete professional electronic face questions , including the number of electric-mode single-chip, and so on. . . . . . . . . . .
First, analog circuit
Kirchhoff Theorem 1 What is? (Shilan Microelectronics)
Kirchhoff's current law is a law of conservation of electric charge, equal to the charge flowing into a node in a circuit of the charge and the discharge of the same node.
KVL is a conservation of energy, i.e., voltages and the zero loop in a loop.
2, the capacitor plates formula (C = εS / 4πkd). (unknown)
3, the basic triode characteristic curve. (unknown)
4, the concept of the feedback circuit is described, include their application. (Shilan Microelectronics)
5, the kind of negative feedback (feedback voltage shunt, series feedback current, voltage and current shunt feedback series feedback); negative feedback advantages (reduced sensitivity of the amplifier gain, output resistance and the input resistance change, and to improve the linearity of the amplifier nonlinear distortion, effectively extending the pass band of the amplifier, the automatic regulation) (unknown)
6, what is the purpose of the amplifier circuit is frequency compensation, which method? (Shilan Microelectronics)
7, the frequency response, such as: how is considered stable, how to change the frequency response curve of several methods. (unknown)
8, the operational amplifier is given a check points, how the phase compensation and the compensated Videos Bode plot. (Bump)
9, the type of the basic amplifying circuit (voltage amplifier, a current amplifier, transconductance amplifier and the transimpedance amplifier), the advantages and disadvantages, especially the widely used reasons differential structure. (unknown)
10, a differential circuit is given, and to tell the output voltage Y Y-, seeking common mode and differential mode components components. (unknown)
11, two inputs of the error amplifier painted pipe. (Bump)
12, draw the discharge circuit schematic configuration transported by addition, subtraction, differentiation, integration calculation. And draw a transistor stage operational amplifier circuit. (Shilan Microelectronics)
13, an operational amplifier with an amplifier 10x. (unknown)
14 gives a simple circuit, so you analytical characteristics (that is integrating circuit) of the output voltage, and determining the output of a point rise / fall time. (Infineon written questions)
15, a resistor R and a capacitor C connected in series, the input voltage and output voltage between the R and C are the voltage on the C-R and the voltage, the frequency spectrum required braking circuit both the input voltage, the two circuits is determined what is high-pass filter, a low pass filter Ho. When RC q, as well as the clock delay <, write the greatest determinant of the clock, and gives expression. (VIA VIA 2003.11.06 Shanghai written questions)
18, talk about the static and dynamic advantages and disadvantages of the timing simulation. (VIA VIA 2003.11.06 Shanghai written questions)
19, one of four Mux, wherein the second level signal is a key signal how to improve timing. (VIA VIA2003.11.06 Shanghai written questions)
20, a given level of FIG gate, gave the transmission delay of each door, ask what the critical path is also asked given input, so that the output is dependent on the critical path. (unknown)
21, Kano logics FIG digital circuit simplification, a timing (synchronous asynchronous difference), there are several triggers (differences, advantages) full adder and the like. (unknown)
22, write logic expression so that Karnaugh map. (VIA VIA 2003.11.06 Shanghai written questions)
23, simplify F (A, B, C, D) = m (1,3,4,5,10,11,12,13,14,15) and. (VIA)
24、please show the CMOS inverter schmatic,layout and its cross sectionwith P-well process.Plot its transfer curve (Vout-Vin) And also explain the operation region of PMOS and NMOS for each segment of the transfer curve? （威盛笔试题circuit design-beijing-03.11.09）
25、To design a CMOS invertor with balance rise and fall time,please define the ration of channel width of PMOS and NMOS and explain?
26, why a standard width to length of the inverter P in width to length ratio of the pipe than the pipe is larger than N? (Shilan Microelectronics)
27, with mos tube Dachu a two-input NAND gate. (ALi electronic written)
28、please draw the transistor level schematic of a cmos 2 input AND gate and explain which input has faster response for output rising edge.(less delay time)。（威盛笔试题circuit design-beijing-03.11.09）
29, drawn NOT, NAND, NOR symbols, the truth table, there is a transistor level circuit. (Infineon written examination)
30, CMOS draw the map, draw a tow-to-one mux gate. (VIA VIA 2003.11.06 Shanghai written questions)
31, with a mux and a second election XOR inv. (Philips - Datang written)
32, Y = cmos shown a circuit diagram of the A * BC. (Section broad questions)
33, and cmos logic circuit implementation ab cd. (Philips - Datang written)
34, draw the transistor level circuit diagram of a CMOS circuit, to achieve Y = A * BC (DE). (Shilan Microelectronics)
35, using 4 to 1 to achieve F (x, y, z) = xz yz '. (unknown)
36, to an expression f = xxxx xxxx xxxxx xxxx with the minimum number of NAND gate implementation (actually simplification).
37, a simple schematic is given by a plurality of NOT, NAND, NOR compositions, the points plotted waveform from the input waveform. (Infineon written examination)
38, in order to achieve a logical (A XOR B) OR (C AND D), please choose one of the following logic, and why? 1) INV 2) AND 3) OR 4) NAND 5) NOR 6) XOR Answer: NAND (Unknown)
39, NAND gates, etc. full adder design. (Huawei)
40, given two gates allow you to analyze similarities and differences. (Huawei)
41, a simple circuit implementation, when A is input, the output waveform is ... B (Microelectronics Shilan)
42, A, B, C, D, E vote, the minority obey the majority, is the output F (i.e., if the number of A, B, C, D, E in a ratio of multi-0, then the output is 1 F, otherwise F is 0), realized with a NAND gate, the input number is not limited. (unknown)
43, the waveform represented by D flip-flop function. (ALi electronic written)
44, take the edge flip-flop with a transfer gate and is backward. (ALi electronic written)
45, D flip-flop logic to draw them. (VIA VIA 2003.11.06 Shanghai written questions)
46, the structure shown in FIG DFF realize purposes verilog. (VIA)
47, drawn to a CMOS circuit diagram of the D latch and layout. (unknown)
48, the difference between D and D flip-flop latch. (New hardware too Interview)
49, latch outlined similarities and differences between the filp-flop. (unknown)
50, LATCH and DFF concepts and distinction. (unknown)
51 difference, latch and register, and why now multi-purpose register. How behavioral description generated latch. (Nanshan bridge)
52, a D flip-flop circuit to be a half frown. Asked what is the state of FIG. (Huawei)
53, the logic circuit Draw divide-by-2 flip-flop implemented with D? (HW written)
54, how to use D flip-flops, and frequency divider circuit two NOR gates? (Eastcom written)
55、How many flip-flop circuits are needed to divide by 16? (Intel) 16分频？
56, an adder design with a filp-flop and logic-gate, the input and carryin current-stage, and the output carryout next-stage. (Unknown)
57, a D flip-flops to be 4-ary counting. (Huawei)
58, implement an N-bit Johnson Counter, N = 5. (Nanshan bridge)
59, you are familiar with the design approach to design a preset initial value of 7 binary cycle counter, 15-ary it? (Shilan Microelectronics)
60, digital circuit design will of course Q Verilog / VHDL, designed as a counter. (unknown)
61, BLOCKING NONBLOCKING assignment difference. (Nanshan bridge)
62, write verilog module asynchronous D flip-flop. (ALi electronic written)
module dff8(clk , reset, d, q);
input clk;
input reset;
input [7:0] d;
output [7:0] q;
reg [7:0] q;
always @ (posedge clk or posedge reset)
if(reset)
q <= 0;
else
q <= d;
endmodule
63, to achieve the Verilog description of a divide-by-2 D flip-flop? (HW written)
module divide2( clk , clk_o, reset);
input clk , reset;
output clk_o;
wire in;
reg out ;
always @ ( posedge clk or posedge reset)
if ( reset)
out <= 0;
else
out <= in;
assign in = ~out;
assign clk_o = out;
endmodule
64, programmable logic devices more and more important in modern electronic design, ask: a) you know what a programmable logic device? b) Trial VHDL or VERILOG, ABLE described 8-bit D flip flop logic. (HW written)
PAL，PLD，CPLD，FPGA。
module dff8(clk , reset, d, q);
input clk;
input reset;
input d;
output q;
reg q;
always @ (posedge clk or posedge reset)
if(reset)
q <= 0;
else
q <= d;
endmodule
65, describe four full adder with HDL, 5 frequency dividing circuit. (Shilan Microelectronics)
66, to write a piece of code with VERILOG or VHDL, to achieve 10 binary counter. (unknown)
67, to write a piece of code with VERILOG or VHDL, to achieve the elimination of a glitch. (unknown)
68, the subject of a state machine implemented in verilog (though this picture of the state machine is really rather poor, easily misunderstood). (VIA VIA 2003.11.06 Shanghai written questions)
69, describes a traffic signal design. (Shilan Microelectronics)
70, draw a state machine to accept 1,2,5-cent machines selling newspaper, each newspaper 5 cents. (ALi electronic written)
71, design a vending machine system, selling soda water, only dropped three kinds of coins, to retrieve the correct amount of money. (1) Draw FSM (Finite State Machine); (2) verilog programming syntax fpga to meet design requirements. (unknown)
72, a design of an automatic beverage vending machines, the beverage 10 cents coins 5 and 10 at the two points, and to consider the change: (1) shown FSM (Finite State Machine); (2) verilog programming Grammar in line with fpga design requirements; (3) design engineering and design tools available general process. (unknown)
73, draw strings can detect the state of FIG. 10010, and verilog Achieving. (VIA)
74, realized with FSM 101101 sequence detection module. (Nanshan bridge)
a is an input terminal, an output terminal b, if a continuous input is output as a 1101 b, and 0 otherwise. For example a: 0001100110110100100110
b： 0000000000100100000000
Draw state machine; describe its state machine with RTL. (unknown)
75, (the write state machine sub-state) with verilog / vddl stream specific character string detection. (Philips - Datang written)
76, a write fifo controller (including empty, full, half-full signal) with verilog / vhdl. (Philips - Datang written)
77, a user need for a conventional integrated circuit product, the product is required to achieve the following functions: y = lnx, wherein, x is an integer of 4-bit binary input signal. y is a binary fractional output, requires two decimal places. Supply voltage is 3 ~ 5v assume that the company, after receiving the project, handed over to you to be responsible for the product design, try to discuss the design of the entire product. (Shilan Microelectronics)
78 difference sram, falsh memory, and a dram? (New hardware too Interview)
79, schematic shows a single tube of DRAM (Western Electric version of "Digital Electronic Technology" by Yang Songhua, Mao Feng official 205 Figure 9 -14b), to ask you is there any way to improve the refresh time, a total of five questions, can not remember a. (Reducing the temperature, increasing the capacitance of the storage capacity) (written Infineon)
80、Please draw schematic of a common SRAM cell with 6 transistors,point out which nodes can store data and which node is word line control? （威盛笔试题circuit design-beijing-03.11.09）
81, nouns: sram, ssram, sdram noun IRQ, BIOS, USB, VHDL, SDR
IRQ: Interrupt ReQuest BIOS: Basic Input Output System USB: Universal Serial Bus
VHDL: VHIC Hardware Description Language SDR: Single Data Rate
VCO abbreviation (VCO). Abbreviation of dynamic random access memory (DRAM).
Glossary boring English acronym fills, such as PCI, ECC, DDR, interrupt, pipeline IRQ, BIOS, USB, VHDL, VLSI VCO (voltage controlled oscillator) the RAM (Dynamic Random Access Memory), FIR IIR DFT (Discrete Fourier Transform) or Chinese, such as:. a quantization error histogram c b balance.
Two, the IC design basis (process, technology, layout, device)
1, our company's products are integrated circuits, please describe your understanding of integrated circuits, integrated circuits are some related content (such as clear analog, digital, bipolar, CMOS, MCU, RISC, CISC, DSP, ASIC, FPGA, etc. concept). (Shilan micro-interview questions)
2, FPGA and ASIC concept, the difference between them. (unknown)
The answer: FPGA is programmable ASIC.
ASIC: Application Specific Integrated Circuit, which is a circuit for special purpose, specially designed and manufactured to a user. According to a user's specific requirements, can be developed at low cost, short delivery lead times of full-custom, semi-custom integrated circuit. Compared with other ASIC gate array (Application Specific IC), which in turn have a short design cycle development, design and manufacture of low cost, advanced development tools, standard products without testing, quality inspection and a real-time online, etc.
3, what is OTP films, mask films, what difference between the two? (Shilan micro-interview questions)
4, you know the expression of integrated circuit design, which has several? (Shilan micro-interview questions)
5. Describe your understanding of the integrated circuit design process. (Shilan micro-interview questions)
6, programmable logic device, FPGA, etc. Brief design process. (Shilan micro-interview questions)
7, IC design flow to the front end and the rear end of the eda tools. (unknown)
8, the design flow from RTL synthesis between the tape out, and wherein each of the listed tool used in step. (Unknown)
9, Asic the design flow. (VIA VIA 2003.11.06 Shanghai written questions)
10, pre-write asic design process and corresponding tools. (VIA)
11, IC design flow preceding paragraph, write-related tools. (ALi electronic written)
First introduced to the IC development process:
1) Code Input (design input)
Using vhdl or verilog language to complete the functional description of the device, the code generating hdl
Language input tool: SUMMIT VISUALHDL
MENTOR RENIOR
Graphics: composer (cadence);
viewlogic (viewdraw)
2) Circuit Emulation (circuit simulation)
The logic simulation vhd previous code, to verify the correct functionality described
Digital circuit simulation tools:
Verolog： CADENCE Verolig-XL
SYNOPSYS VCS
MENTOR Modle-sim
VHDL : CADENCE NC-vhdl
SYNOPSYS VSS
MENTOR Modle-sim
Analog circuit simulation tool:
***ANTI HSpice pspice，spectre micro microwave: eesoft : hp
3.) logic synthesis (synthesis tools)
Logic synthesis tools can design vhd code is converted to the corresponding certain technical means of gate level circuits; the door of the primary simulation that are not considered in the (gates delay) using reversed to the gate-level netlist, the return circuit simulation stage then simulation. The final simulation results netlist generated called physical netlist.
12. Please describe briefly the whole back end of the design process? (Shilan micro-interview questions)
13, if exposed to automatic placement and routing? Say twelve kinds of tools. What are the basic elements of automatic placement and routing needs? (Shilan micro-interview questions)
14, describe your understanding of the integrated circuit technology. (Shilan micro-interview questions)
15, to name a few typical IC process. A process often referred to 0.25,0.18 refers to what? (Shilan micro-interview questions)
16. Please describe the status of the domestic process. (Shilan micro-interview questions)
17, semiconductor technology, which is doped with ways? (Shilan micro-interview questions)
18, describes the process of the CMOS circuit latch-produced and the final result? (Shilan micro-interview questions)
19, explaining latch-up phenomenon and Antenna effect and its preventive measures. (Unknown)
20, what is Latchup? (Section broad questions)
21, what is the narrow channel effect? (Section broad questions)
22, what is NMOS, PMOS, CMOS? What is an enhanced, depletion mode? What is PNP, NPN? What are their differences? (Shilan micro-interview questions)
23, silicon gate COMS process is done in the N-well or P N pipe tube connected to the well potential of the N-well requirements? (Shilan micro-interview questions)
24, the CMOS transistor shown in FIG CROSS-OVER (should be a vertical sectional view), given all possible transmission and transfer characteristics. (Infineon written questions)
25 to interver example, to write the N-well CMOS process flow, and cross-sectional view shown in FIG. (Section broad questions)
26、Please explain how we describe the resistance in semiconductor. Compare the resistance of a metal,poly and diffusion in tranditional CMOS process.（威盛笔试题circuit design-beijing-03.11.09）
27, description mos half work in what area. (Bump topics and interview)
28, nmos cross-sectional view of the p-bulk Videos. (Bump topics and interview)
29, write schematic note (?), The better. (Bump topics and interview)
30, parasitics in ic design How to overcome and use. (unknown)
31, too low-level physical characteristics of MOS transistors generally do not feel the General Assembly as written interview questions, because all physical microelectronics, formula derivation too Roseau, unless the topic of the interview is an old pedant. IC design, then need to be familiar software: Cadence, Synopsys, Avant, UNIX course will also probably operating.
32, unix command cp -r, rm, uname. (ALi electronic written)
____________________________________________________________
Third, SCM, MCU, computer theory
1, a brief description of the main constituent modules SCM system, and illustrates the data flow and control flow to flow between the modules. Design principles outlined microcomputer application system. (Shilan micro-interview questions)
2, shown with 8031 2716 (2K * 8ROM) FIG connection, requires three - eight decoder, 8031 is the P2.5, P2.4 and P2.3 participate decoding, the base address range 3000H-3FFFH . The 2716 there is no overlap address? What basis that? If so, to write each piece overlapping address ranges 2716. (Shilan micro-interview questions)
3, 8051 with a design with a 8 * 16 digital keyboard plus eight driving pipe principle (positive co) FIG. (Shilan micro-interview questions)
4. What is the meaning of the PCI bus? What are the main features of the PCI bus is? (Shilan micro-interview questions)
5, interrupt the concept? Brief interruption of the process. (Shilan micro-interview questions)
6, such as several single-chip interrupt / type, compiled interrupt routine attention to the problem; (Unknown)
7, to use an open-loop speed control system controlling the rotational speed pulsed DC motor, completed by the program 8051. Simple principle is as follows: P3.4 controlled by the duty cycle of the output pulse speed, larger the duty cycle, the faster the speed; and the duty ratio set by the K7-K0 eight switches, directly connected to the port P1 (the toggle switch when the bottom is "0", when the above toggle is "1", composed of a N-bit binary number), the duty cycle required to N / 256. (Shilan micro-interview questions)
The following procedures counting method to achieve this function, please add complete spare part.
MOV P1，#0FFH
LOOP1 ：MOV R4，#0FFH
--------
MOV R3，#00H
LOOP2 ：MOV A，P1
--------
SUBB A，R3
JNZ SKP1
--------
SKP1：MOV C，70H
MOV P3.4，C
ACALL DELAY: This delay routine slightly
--------
--------
AJMP LOOP1
8, the microcontroller is not running after power, what we should first check? (Eastcom pen questions)
9, What is PC Chipset? (ALi electronic written)
Chip set (Chipset) is a core part of the board, arranged in different positions on the motherboard, usually divided into Northbridge and Southbridge. Northbridge provide the type and frequency of the CPU, memory type and maximum capacity ISA / PCI / AGP slots, ECC error correction support. Southbridge provides, the RTC (real time clock controller) / 33 (66) supports KBC (keyboard controller) the USB (Universal Serial Bus), Ultra DMA EIDE data transmission and ACPI (Advanced Energy Management), etc. . Wherein Northbridge plays a dominant role, also called the main bridge (Host Bridge).
In addition to the most common north and south bridge structure, currently more advanced chipset forward to accelerate the development of hub architecture, Intel's 8xx series chipset is representative of such chipsets will some subsystems, such as IDE interface, sound, MODEM and USB direct access to the main chip, can be provided PCI bus bandwidth wider than double, reaching 266MB / s.
10, said that if done on a resume like cpu, cpu will be asked, such as how it works, pipeline problems and the like. (unknown)
11, the basic components of a computer and their respective roles. (Eastcom pen questions)
12. Draw a microcomputer interface circuit, a logic diagram of a typical computer interface input device (data interface, a control interface, the memory / buffer). (HW written)
13, the main part of the cache or something. (VIA VIA 2003.11.06 Shanghai written questions)
14, synchronous asynchronous transfer difference (unknown)
15, a serial communication with the synchronous communication similarities and differences, and to compare. (Huawei face questions)
Fourth, Signals and Systems
1, the voice frequency is generally 300 ~ 3400HZ, if a signal sampled and its distortion, the minimum sampling frequency should be? The use of a sampling frequency 8KHZ, and using 8bit PCM coding, the amount of data stored in a second signal how much? (Shilan micro-interview questions)
2. What Nyquist's law, how the digital signal into an analog signal. (Huawei face questions)
3, if the bandwidth of the analog signal is 5khz, use a sampling rate of 8K, how do? lucent) two-way?
4, the signal system: the relationship between the time and frequency domains. (Huawei face questions)
5, the time domain signal is given, find the DC component. (unknown)
6, a time domain signal is given, the requirements (1) to write the frequency component, (2) to write its Fourier transform series; (3) when the waveform after filtering out the higher harmonics leaving only the first harmonic , the output waveform shown filtered. (unknown)
7, sketch continuous rectangular wave and the continuous sinusoidal signal (Fig both) the Fourier transform. (Infineon written questions)
8, Laplace transform and Fourier transform of expression and contact. (New too hardware face title)
____________________________________________________________
Five, DSP, embedded, software, etc.
1. Please describe your familiar with the block diagram of a practical digital signal processing system, and a brief analysis; if not, you can also design your own with a simple digital signal processing systems, and describe its function and use. (Shilan micro-interview questions)
2, classification and structural characteristics of the digital filter. (Shilan micro-interview questions)
3, the similarities and differences IIR, FIR filter. (New too hardware face title)
4, the Laplace transform Z-transform equation and similar things, such as the book casually looking .h (n) = -. A * h (n-1) b * δ (n) a request h (n) z-transform ; B asked whether the system is a stable system;. C write FIR digital filter difference equations;. (unknown)
5, DSP and general-purpose processor What is the difference in structure, please briefly draw you are familiar with a DSP structure. (Xinwei dsp software interview questions)
6, talk about the definition of fixed-point DSP and floating point DSP (or tell the difference between them) (Xinwei dsp software interview questions)
7, talk about your understanding of circular addressing and bit-reversed addressing sequence. (Dsp software is inscribed Xinwei)
8, please write [-8,7] twos complement and offset binary code. 0.5 and -0.5 is shown by Q15. (XINWEI dsp software interview questions)
9, DSP structure (Harvard architecture); (Unknown)
10, the embedded processor type (e.g. the ARM), operating system type (Vxworks, ucos, winCE, linux), operating system CS biasing direction, and in which stresses the article CS; (unknown)
11, there is a LDO chip will be used to power mobile phones, you need to evaluate him, how would you design your test project?
12, a program in an embedded system (200M CPU, 50M SDRAM) has been optimized, and for a system to zero (300M CPU, 50M SDRAM) Are also need to optimize? (Intel)
13, please briefly describe the basic principles of HUFFMAN coding and its basic implementation. (Shilan micro-interview questions)
14, say seven layer OSI network protocol four (four arbitrary). (Shilan micro-interview questions)
15, A) (Shilan micro interview questions)
＃i nclude
void testf(int*p)
{
*p =1;
}
main()
{
int *n,m[2];
n=m;
m[0]=1;
m[1]=8;
testf(n);
printf("Data v alue is %d ",*n);
}
------------------------------
B)
＃i nclude
void testf(int**p)
{
*p =1;
}
main()
{int *n,m[2];
n=m;
m[0]=1;
m[1]=8;
testf(&n);
printf(Data v alue is %d",*n);
}
The results below are program A or program B?
Data v alue is 8
So what is the result of another section of the program?
16, ordering that the fastest way? (Huawei face questions)
17, write two sorting algorithms, ask which is better? (VIA)
18, a simple request compiled n! Program. (Infineon written questions)
19, written in a programming language n! Algorithms. (VIA VIA 2003.11.06 Shanghai written questions)
20, written in C language a recursive algorithm for N! ; (Huawei face questions)
21, a C to a function of, on strings and arrays for errors; (Huawei face questions)
22, the firewall is how to achieve? (Huawei face questions)
23, what areas you are familiar with programming? (Huawei face questions)
24, bubble sort of principle. (New too hardware face title)
25, operating system functions. (New too hardware face title)
26, learned the language and the development of computer systems. (New too hardware face title)
27, surrounded by a farmer found, but the same ratio of a square fence save four stakes rectangular area. The number of the same number of pile and sheep but less than 36 square fences, sheep asked how many? (VIA)
28, C language statistics the number of times a cell in a .v file called (the subject really bt) (VIA VIA2003.11.06 Shanghai written questions)
29, write a driver to control the phone Mada Zhen child in C language. (Granville)
30, to achieve a string comparison and identification procedures or perl TCL / Tk. (unknown)
31, gives a stack structure, after seeking interrupt display the results, mainly to test the stack pressed into the return address is stored in the low-end or high-end address. (unknown)
32, a number of DOS commands such as displaying the file, copy, delete. (unknown)
33, a design class, such that any form of derived classes, no matter how defined and implemented, can not produce any object instance. (IBM)
34、What is pre-emption? (Intel)
35、What is the state of a process if a resource is not available? (Intel)
36, three float a, b, c; Q value (ab) c == (ba) c, (ab) c == (ac) b. (Intel)
37, to fill in the blank reverse a linked list. (Lucent)
38, x ^ 4 a * x ^ 3 x ^ 2 c * xd do need at least a few times multiplication? (Dephi)
____________________________________________________________
Six, subjective questions
1. What characteristics do you think you are engaged in research and development work? (Shilan micro-interview questions)
2. say your greatest weakness and improved methods. (VIA VIA 2003.11.06 Shanghai written questions)
3, tell your ideals. Say what you want to achieve. English title is out, use English to answer. (VIA VIA 2003.11.06 Shanghai written questions)
4, will be divided into several researchers research, understanding of protocols and algorithms (mainly in the communication network, voice compression image aspect), the electronic research system solutions, with MCU, DSP programming circuit function, an ASIC design circuit design (including MCU, DSP itself), circuit design of function modules (including analog circuits and digital circuits), the rear end of the integrated circuit design (mainly refers to the synthesis and automatic placement and routing technology), Research and technology interface integrated circuit design.
You want to study what aspect do? (You can select multiple directions. In addition, it has been engaged in related research and development can describe your research experience). (Shilan micro-interview questions)
5, please talk about the general idea of a system design. For this idea, what do you think should have the knowledge? (Shilan micro-interview questions)
6, you will imagine a complete electronic circuit design program. Please describe using EDA software (e.g., of PROTEL) design (including schematic and PCB) to prototype debug the entire process. In all sectors should pay attention to what issues? Stable, the capacitance of the selected power, and the size of layout. (HW written)
Reprinted from the article: http://www.pythonheidong.com/blog/article/2868/