Unit Review

Review Unit (record important part)

Introduction: Because people demand for certain aspects of life, began to manufacture something, something easy to use and role is a plus, things began to gain popularity, every thing is progressive, so when manufacturing is to know what is , then why had the idea to start continuous transformation, on the introduction of more small things, identify problems, solve problems, something new. Problems have always been, the problem has not been fully resolved, because only by means of something else and make this issue to maximize small. So we have to learn to know the what, why, how can, how will use, how to further improve. (The following text is taken from "cold autumn round Gui," the blog): studied interrupted, 8259A , protected mode addressing, and so on? Reflected in the operating system, in order to achieve process scheduling, interrupt you use the clock, will be used to interrupt you write 8259A control program; in order to achieve real mode to protected mode switching and protection programming mode, you have to understand processor segment protection mechanism . Before learning this course, this course must first forget the name of " computer " words. Each lesson, each course will introduce a phase circuit. From simple to complex, from the switch to the ALU . Each stage made out of something looks and " computer " does not matter, except that they can store and operations. But it will clearly understand what each stage is actually made out of absolutely no " memory " and " operation "Features. They are just a state of the circuit, or by a signal, another portion of the control circuit state. Due to very simple and very easy to figure out how this thing works. Finally everything makes up a CPU time, as you lie on the floor puzzle fight, fight after the last one got the feeling of looking down. You will understand how the various high and low gate into data, on the screen becomes colorful program. This is called the " principle " . In fact, a gate had no idea what they are doing, but in accordance with the electrical characteristics of the high into low, low level into the high level. It is these different abstract state 0 and 1 concepts, which then produces a " logic gate " . And use this to express the logical operation, logical operations and then use these values to represent a binary operation, then a combination of these operations together with a set switch to start, there is an instruction, which eventually becomes a simple circuit the CPU . The whole process is just one level of abstraction. The upper layer depends on the function and significance of the lower offer, completion itself while providing a higher level of abstraction. Finally, you dug from above, the bottom layer could not find anything 0 or 1 . Including operating systems and protocols, the vast majority of computer-related things are so out of layers of abstraction. This is the " computer ", " composition " of " principle " .) ( The introduction is completed )

 

 

 

            Personal summary

1. Computer by the arithmetic unit, a memory, a controller, the I / O components.
2. Instruction by the operation code and address code consisting of sequentially stored in the memory.
3. The system bus means between the internal bus of the chip, such as registers and registers. The system bus means a CPU, main memory, the I / O information of the transmission line between the major components of the apparatus.
4. Bus control lines ( . 4 stages):

Application allocation phase: application by the need to use the bus master module via the bus arbitration body decided to use the bus right next transmission period granted to certain applicants.

Addressing phase: obtaining the right to use the bus master module issues present a secondary access address obtained from the module and the order, starting from participating in the transmission module.

Data Transmission Phase: master and slave module data exchange, the number of emitted by the source module, a destination module flows through the data bus.

Closure: For information on the main module are removed from the system bus, let the bus use right.

Bus communication control to solve the problem: how to communicate both the beginning and end of transmission is known transport, communication and how to coordinate how the two sides cooperate.

Synchronous communication (master, the sync module is mandatory, a predetermined time to complete)

Asynchronous communication (by way of response, i.e., three-way handshake, when the master module issues a request ( the Request time) signal, waits until "response (from the module is fed back Acknowledge after)" signal, before starting communication, it requires primary and adding two from between the modules Article response line (interactive handshake signal line ( Handsharking )).

Asynchronous communication is not divided into interlocking, semi interlock interlocks (most common).

( In the front-end development, Ajax , or Asynchronous js and xml , is a web development technology to create interactive web applications. The WebSocket is HTML5 , a new protocol, the browser and the server to achieve full-duplex communication. Essence is to by HTTP HTTPS / protocol for exchanging data to create a star after the handshake TCP connection, the server and the client through this TCP connection for real-time communication )

1. Random access memory ( RAM ) Shutdown to restart the loss of data , read-only memory ( ROM ) Shutdown to restart the data is not lost.

( Practical knowledge ) ram is random access memory, which is memory to run, the relevant data is stored after the mobile phone software is running and running, so the ram and run software-related, the greater the ram, the phone run faster, run software the more. However, since the ram is a random access memory, so after shutdown ram stored data will not be saved is equivalent to the computer's hard disk .rom role, now when talking about the storage capacity of the mobile phone basically means rom capacity, it usually points into two parts, one is occupied by the system, a small user operability; the other is user discretionary storage space, the equivalent of a computer hard drive, can store the phone software, user files (photos, video, etc.).

A memory divided into the main memory, secondary memory, a buffer memory.

Buffer - level main memory (speeds approaching cache, main memory above) mainly to solve the CPU and main memory speed mismatch.

Main memory - Style capacity secondary memory storage system solution.

It determines the bandwidth of the memory in the memory as the center of the machine to obtain the transmission speed information. Measures: 1, to shorten the access cycle ;

2 , memory word length increases, so that each access cycle read / write more binary bits;

3 , to increase the bank.

Calculated: Bandwidth = per access cycle to access bits / access cycle. The access cycle is 500ns , each access cycle access 16 -bit, then its bandwidth is 32M bit / S .

1. Refresh: essentially the original stored information read out, then the original message is formed by the refresh and rewrite amplifier regeneration process.

Concentrated Refresh: refresh cycle in a predetermined concentration for a period of all the memory cells are refreshed line by line, read and write operations must be stopped at the moment.

Dispersion Refresh: refresh rows of memory cells for each dispersed into each memory cycle.

Asynchronous Refresh: are binding mode of the first two, it can shorten the "dead time", but also make full use of the maximum refresh interval of 2ms features.

7. The  memory and the CPU is connected to

Step
1, address line connector
2, connected to the data line
3, write command line connecting
4, is connected to the chip select signal
5, selecting memory chips
6, consider the timing with load, etc. (considering practical applications)

 

 

1. Measures to improve memory access speed

Looking for a high speed element, a hierarchy, main memory adjustment structure.

1. A cache ( occurs between the CPU and main memory) to (I / O device to the main memory is higher than the level of CPU memory access request, CPU causes waited in vain, to reduce the working efficiency).

Cache appears (to improve the speed of main memory will always keep up with the development of the CPU), the CPU can not directly access memory, cache and exchanging information.

Local access procedures: instructions and data in the memory is stored in a row, the address of the instruction and data distribution is not random, but the relative clustering, so that when the CPU executes the program, with a relative access memory limitations. (1) write-through method: write data has been written to both the write cache memory, main memory and it can ensure consistency of data Cache, but increased memory access times; (2) write-back: only the write data Cache memory data write without writing, when only Cache data is swapped out written back to main memory. We know, CPU to run the program one instruction is executed one instruction, and instruction addresses tend to be continuous, meaning that when the CPU accesses memory in a short period of time tend to focus on a local, this time may be I met with some need to repeatedly call a subroutine . Computer at work, these subroutines into active memory is much faster than the Cache. CPU when accessing memory, first determine whether you want to access content in the Cache, if it is called a "hit", and the CPU calls the content directly from the Cache; otherwise, it is called "miss", but to CPU memory required to call a subroutine or instructions. CPU can only read out the contents directly from the Cache, which may be written directly to the content. Since Cache access rate is quite fast, so that the CPU utilization rate greatly increased, thereby enabling the overall system performance can be improved.

I / O task: the program compiled by the user or host data input;

The calculation result is supplied to the user; and input output system to achieve coordination of the work of the host.

Unified addressing: the I / O address as a part of the memory address.

Not unified addressing: I / O addresses and memory addresses are separate, so access to the I / O device must have a dedicated I / O instructions. It does not affect the capacity of the main memory.

Different interfaces and ports, the port interface circuit means of some of the registers, these registers are used to store data information and control information wanted, state information. A plurality of ports coupled to corresponding control logic composition interfaces.

Interface function: Function Location transmitting commands, data, reflects the I / O device is operating.

 

Interrupt: computer during the execution of the program, when an abnormal situation or special circumstances, the computer stops execution of the current program, the steering handle these exceptions or special cases, after the end of the process returns to existing discontinuities, continue the original program.

I / O interrupts: When the device is ready, do not do unnecessary CPU wait while continuing to enforce existing procedures, only when the I / O device is ready to make requests to the CPU, then pause the current program is transferred to interrupt the CPU I / O service program.

Condition: the I / O interface to be configured of hardware lines:

Triggers an interrupt request, interrupt mask trigger, queuing, interrupt vector address means is formed, consisting essentially of program interrupt interface circuit embodiment.

Role (in order to meet I / O devices low operating speed, deal with emergencies, real-time control)

Interrupt service process: to protect the site (breakpoint to save the program, and save the contents of general-purpose registers and status register)

              Interrupt service (equipment service)

Recovery site

Interrupt return

Computer during the processing of an interrupt request, there are new interrupt (interrupt source level higher), to deal with the phenomenon of computer called the interrupt nesting (multiple nesting). Not the (singlet interrupt).

Interrupt overcome procedural query the CPU "stepping" phenomenon, to achieve a work in parallel CPU and I / O, improve resource utilization of the CPU.

 

DMA (program will interrupt the main program and the server program seize the CPU, so that more efficient CPU), DMA between the main memory and the interface has a data path, thus exchanging data without going through CPU.

DMA to main memory method of exchanging data:

Stop CPU access main memory

Cycle steal (steal)

DMA and CPU access alternately

DMA interfaces:

Main memory address register ( the AR)

Word counter ( WC)

Data buffer register ( BR)

DMA control logic

Interrupt mechanism

Address register ( DAR)

Working procedure: preprocessing, data transfer, the post-processing.

Program interrupt mode (there is an exception event processing function)

DMA (for transmitting large quantities of data)

The original binary code , anti-code and complement :

• Truth values : 　　a positive number with the number of "+" indicates , negative with "-" indicates , is the true value of the number
• Number of machines : 　　In 0 notation integer , with 1 represents the negative sign , and each value is also used a 0,1 expressed , the number of such machines are also called machine code called number
• Original code : 　　the number of bits of the original code symbols representing a machine with 0 and a number represents a sign , and the remaining represents a number itself
• Anti-code :
  • For the same code and their anti-positive original code
  • For a negative sign bit which is inverted to the original code of the same value you inversion i.e. 0 becomes 1, 1 becomes 0
• Complement :
  • For the same positive number which is the complement of the original code
  • For negative two's complement sign bit of the original code is not changed , the value you negated , the end plus 1

Addressing mode: data address determining section, and a method of instruction the instruction address to be executed next.

(Followed by a lot of addressing modes, the assembly language instruction to a predetermined address of a lot of symbols)

Throughput refers to the network, device, port, a virtual circuit or other facility , successfully transmitted per unit time of data amount ( in bits, bytes measurement, packets, etc. ) . Usually they prefer to use " throughput " the word to represent the performance of a test system ( using test tools to test ) . Thus, because the realization of the influence of various inefficiencies, so that the section of bandwidth is 10Mbps pair of nodes of a link connection can only be achieved 2Mbps throughput. This means that an application on the host can be 2Mbps transmit data to another host speed.

Said bandwidth is the maximum rate , said throughput rate is a certain time. But can not exceed the maximum throughput rate.