CMI coding and NRZ is implemented with FPGA code

NRZ

NRZ refers to the NRZ (NRZ, Non-Return to Zero)

CMI

CMI (Coded Mark Inversion) code is a code mark inversion abbreviation, similar biphasic code, it is also a two-level bipolar codes. Coding rule which is "1" alternately with the code "11" and "00" indicates two yards; "0" represents a fixed code "01."

Uncertain correctness of code, just a thought

 

1  ///////////////////////////////////////////////// //////// // 
2  //   Module1 Test (CLK, OUT1 of, OUT2 of the, OUT3 of, CLK_1, CLK_2, CLK_3); 
. 3  Module1 Test (CLK, OUT1 of, OUT2 of the, OUT3 of);
 . 4  INPUT CLK; // statement hardware input clock signal 
. 5  
. 6  output OUT1 of, OUT2 of the, OUT3 of; // declare three outputs 
. 7  
. 8  REG OUT1 of = . 1 ' B0,. 1 = OUT2 of the ' B0, OUT3 of = . 1 ' B0; // initializes three outputs 
. 9  
10  REG [ . 4 : 0 ] = counter1 . 4 'd0; // initialize output timing learning number counter 
. 11  REG [ . 4 : 0 ] = counter2 2 ' d0; // initialize cmi code counter 
12 is  REG [ . 4 : 0 ] = counter3 . 4 ' D0; 
13 is  
14  REG [ . 1 : 0 ] = T1 2 ' B00; 
15  REG T0 = . 1 ' B0; // the amount of encoded intermediate 
16  REG r0 of = . 1 ' B0, R1 =. 1 ' B0, R11 = . 1 ' B0 // decoding intermediate quantity 
. 17  
18 is reg clk_1= 1'b0;
19 reg clk_2= 1'b0;
20 ////////////////////////////////////////////////////////////
21 always @(posedge clk)  //产生240k时钟
22     if(counter1 == 3'd7 )
23         begin
24             counter1 <= 3'd0;
25             clk_1 <= ~clk_1;
26         end 
27     else 
28         counter1 <= counter1 + 1'd1;            
29 //////////////////////////////////////////////////////
30 always @(posedge clk)   //产生480k时钟
31     if(counter2 == 2'd3 )
32         begin
33             counter2 <= 2'd0;
34             clk_2 <= ~clk_2;
35         end 
36     else 
37          counter2 <= counter2 + 1'd1;
38 /////////////////////////////////////////////////////////    
39 always @(posedge CLK_1)   // generate NRZ code, student number 0072 
40      IF (counter3 == . 4 ' D14)   
41 is          the begin 
42 is              counter3 <= . 4 ' D0; 
43 is              OUT1 of <= . 1 ' B0; 
44 is          End     
45      the else  
46 is          the begin  
47              Casez (counter3 )
 48                  . 4 ' D1011: OUT1 of <=. 1 ' B1;
 49                  . 4 ' B1000: OUT1 of <=. 1 ' B1;
 50                  default : OUT1 of <= . 1' B0; 
51 is              ENDCASE 
52 is              counter3 <+ = counter3 . 1 ' D1; 
53 is          End       
54 is  //////////////////////////////// //////////////// // 
55  Always @ ( posedge CLK_2) //   the CMI encoder 
56 is      iF (OUT1 of == . 1 ' B0) // when the student number is 0, the output 
57 is          the begin 
58              iF (t0 == 0 ) // because cmi coding 0 to 01 as the two, it takes a flag t0, when t0 is 0, the output of the first 01, t0 is 1, outputs 01 two. 
59                  OUT2 of the <= 0 ;
 60              the else 
61 is                 OUT2 of the <= 1 ;
 62 is              T0 <= ~ T0;
 63 is          End 
64      the else 
65          the begin 
66              IF (T1 [ 1 ] == 0 )
 67  // here similar to the above, because 1 to 00 and 11, alternates, so the flag bit t1 is two, when the student number is 1, the beginning want to output 11, the output is 1 followed by 00 plus 01 is 01, the output is 0,
 68  // and then back again when school number 1, 01 plus 01 10, then the output is 1, the back 10 plus 01 to 11, the output is 1, then again if after adding 01 to 00 
69                  OUT2 of the <= 1 ;
 70              the else 
71 is                  OUT2 of the <= 0 ;
 72              T1 <= T1 + 2 ' B01; 
73 is         End 
74  //////////////////////////////////////////////// ///
 75  Always @ ( posedge CLK_2)    //   the cMI decoder 
76      IF (R11 == . 1 ' B0) // output out2, i.e., the value assigned to the coding cmi r0 and r1, and whichever is found to be 0 the coding result is 0, the result is an encoded result of 1 
77          the begin 
78              OUT3 of <= (r0 of ^ R1); // R11 corresponds here a bit allocation flag out2 because the output of only one bit output out2 Therefore r11 is 0, to the value of r0 of out2, r11 is 1, the value of out2 to R1 
79              r0 of <= out2;
 80              r11 <= ~ r11;
 81          End 
82      the else 
83          the begin 
84              R1 <= out2;
85             r11 <= ~r11;    
86         end
87 
88 endmodule

 

Guess you like

Origin www.cnblogs.com/BugsCreator/p/11264446.html