For example: the ADD R0 [. 6] (i.e., the default is the first operand of the original operand and a destination operand)
The data in the general register R0, is added to the data memory address 6, back to the register R0
The computer has been assumed that the initial value, the value of R0 00000011, PC 0001 the value of the memory address with instructions 10101010 0001 refer,
specifically Detailed procedure:
1. Fetch: instruction address sent to the memory controller, memory read data at a given address, back to the controller
(1) the controller issues a control signal, the PC register contents are transferred to the MAR (also stored in the MAR 0001) via the CPU internal bus
(2) the MAR address to the address bus, at the same time, the control circuit sends a control signal on the control bus, the representative of the operation of read, so that the memory will receive the address register MAR upload address bus sent, and save it to
memory the control logic also receives a signal on the control bus, the operation expressed as read, by the memory address decoder so that it can find the content corresponding to the address storage unit 0001, and transfers the data to which MDR register
(3) memory control logic feedback control bus current transmission state READY to the CPU, while the contents of MDR is transferred to the data bus, with After the CPU in the control circuit detects a control signal on the bus Ready to know the current data on the data bus is ready,
and therefore, the CPU will save the MDR data transfer bus down, then the data must be MDR IR transferred to the register
(4) data from the PC register is updated to the address of the next instruction required to access 0010 (value stage is completed)
2. decoding: the controller analyzes the nature of the operation instruction, the controller issues control signals required for the relevant instruction means
(1) the current data to the instruction register IR decoding means, instruction decoding means in accordance with instructions encoded parsing 10101010 (ADD R0 [6]), whereby the control circuit generates a corresponding control signal sent to the associated member
3. Execute: Controller removed operands from a general register or memory, the controller command computing unit calculates operand of the instruction.
(1) MAR 0110 may be generated (i.e., 6) is similar to a subsequent process stage value, because the last data transfer to be performed in CPUMDR adding, then it will transmit it to the ALU in the Y-register
(2) another operand is stored in R0, R0 so it will transmit data to the other input terminal of the ALU, i.e. the X-register
(3) under the action of the control circuit, ALU calculates the execution contents of XY addition, the results calculated 00000101
4 writeback: the result is written in a general register or memory
(1) the current calculation result is also the output of the ALU Z-register, the control circuit gives a control data corresponding to the Z-register transferred into R0, R0 is the original data of the new results covering
(2) CPU in the PC for the next instruction register
