About NVIC
NVIC is a nested vector interrupt controller, interrupt controls the entire chip-related feature that is tightly coupled with the kernel, is a peripheral cores inside. However, various chip manufacturers have Cortex-M4 core inside the NVIC in the design of the chip when cut, remove the unwanted parts, so that the STM32 NVIC NVIC is a subset of the Cortex-M4.
About NVIC register
Code 17 NVIC structure is defined, from the firmware library header files: core_cm4.h
typedef struct {
__IO uint32_t ISER[8]; // 中断使能寄存器
uint32_t RESERVED0[24];
__IO uint32_t ICER[8]; // 中断清除寄存器
uint32_t RSERVED1[24];
__IO uint32_t ISPR[8]; // 中断使能悬起寄存器
uint32_t RESERVED2[24];
__IO uint32_t ICPR[8]; // 中断清除悬起寄存器
uint32_t RESERVED3[24];
__IO uint32_t IABR[8]; // 中断有效位寄存器
uint32_t RESERVED4[56];
__IO uint8_t IP[240]; // 中断优先级寄存器(8Bit wide)
uint32_t RESERVED5[644];
__O uint32_t STIR; // 软件触发中断寄存器
} NVIC_Type;In the configuration we generally only interrupted by ISER, ICER and IP these three registers, ISER to enable interrupts, ICER for disabling interrupts, IP is used to set the interrupt priority
NVIC interrupt configuration firmware library
| NVIC library functions | description |
|---|---|
| void NVIC_EnableIRQ(IRQn_Type IRQn) | Enable interrupt |
| void NVIC_DisableIRQ(IRQn_Type IRQn) | Disabling interrupts |
| void NVIC_SetPendingIRQ(IRQn_Type IRQn) | Set interrupt hanging from bits |
| void NVIC_ClearPendingIRQ(IRQn_Type IRQn) | Clear Interrupt hanging from bits |
| uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) | Gets hanging from the interrupt number |
| void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) | Set the interrupt priority |
| uint32_t NVIC_GetPriority(IRQn_Type IRQn) | Gets interrupt priority |
| void NVIC_SystemReset(void) | System reset |
Priority Definition
In NVIC has a dedicated register: interrupt priority register NVIC_IPRx (in F429, x = 0 ... 90) to set the priority, IPR width of the external interrupt is 8bit, in principle, each configurable priority external interrupts level from 0 to 255. The smaller the value, the higher the priority. But the vast majority of CM4 chip will be streamlined design that actually reduce support its priority, in F429, using only high 4bit, as follows:
Priority for the expression of this 4bit, has been grouped preemption priority and sub-priority. If there are multiple-interrupt response, to seize the high priority will preempt lower priority preemptive priority to be implemented, if the same preemption priority, it is more child priority. If the preemption priority and the child have the same priority, then, is more their hardware interrupt number, the smaller the number, the higher the priority.
Priority Grouping
Interrupt priority packets by the application of the kernel and peripheral SCB register reset control PRIGROUP AIRCR [10: 8] bits determine, F429 divided into five groups, as follows: = master priority preemption priority.
Set the priority groups may call the library function NVIC_PriorityGroupConfig () implement the relevant NVIC interrupt-related library functions in the library file misc.c and misc.h in.
Interrupt programming
In the configuration of each interrupt when the program generally have three main points:
1, an interrupt is enabled peripherals, related to the specific of each peripheral interrupt enable bits. Such as the serial port interrupt has completed transmission, reception completion interrupt, the serial port associated by the two interrupt control register interrupt enable bit.
2, the initialization NVIC_InitTypeDef structure disposed interrupt priority packets, and the sub-set priority preemption priority, enabled interrupt request.
Initialization Code structure 19 NVIC
typedef struct {
uint8_t NVIC_IRQChannel; // 中断源
uint8_t NVIC_IRQChannelPreemptionPriority; // 抢占优先级
uint8_t NVIC_IRQChannelSubPriority; // 子优先级
FunctionalState NVIC_IRQChannelCmd; // 中断使能或者失能
} NVIC_InitTypeDef;Members concerned initialization structure NVIC us one explain:
1) NVIC_IROChannel: used to set the interrupt source, different interrupt source is not the same, and can not be wrong, even if wrong program does not complain, can only lead to unwanted interruption. Specific members of the configuration structure is defined with reference to IRQn_Type stm32f4xx.h header inside, this structure contains all of the interrupt sources.
Interrupt Source Code structure 20 IRQn_Type
typedef enum IRQn {
//Cortex-M4 处理器异常编号
NonMaskableInt_IRQn = -14,
MemoryManagement_IRQn = -12,
BusFault_IRQn = -11,
UsageFault_IRQn = -10,
SVCall_IRQn = -5,
DebugMonitor_IRQn = -4,
PendSV_IRQn = -2,
SysTick_IRQn = -1,
//STM32 外部中断编号
WWDG_IRQn = 0,
PVD_IRQn = 1,
TAMP_STAMP_IRQn = 2,
// 限于篇幅，中间部分代码省略，具体的可查看库文件 stm32f4xx.h
SPI4_IRQn = 84,
SPI5_IRQn = 85,
SPI6_IRQn = 86,
SAI1_IRQn = 87,
LTDC_IRQn = 88,
LTDC_ER_IRQn = 89,
DMA2D_IRQn = 90
} IRQn_Type;2) NVIC_IRQChannelPreemptionPriority: preemption priority, a specific value to be determined, particularly with reference to the truth table of Table 16 priority packets according to the priority packets.
3) NVIC_IRQChannelSubPriority: child priority, a specific value to be determined according to the priority packets, with particular reference to a truth table of the table 16 priority packets.
4) NVIC_IRQChannelCmd: Interrupt Enable (ENABLE) or disabled (DISABLE). And the operation is NVIC_ISER NVIC_ICER these two registers.
3, program an interrupt service routine
In the startup file startup_stm32f429_439xx.s in our pre-written for each interrupt an interrupt service routine, but these functions are empty interrupt for just initialize the interrupt vector table. The actual interrupt service routine requires us to re-write, write interrupt service routine in our unified stm32f4xx_it.c this library file.
Like the function name on interrupt service routine must be followed by a preset startup file, if wrong, the system can not find in the interrupt vector table entry interrupt service function, jump directly to the start of pre-written documents inside empty function and infinite loop in it, can not achieve interruption.