1. Work users
uboot
2. uboot version 1.1.4
3. The tool chain 2.95.3
step
We take the name as a development board: crane2410, and create their own type of development board in the uboot
Modify Makefile
[uboot@localhost uboot]#vi Makefile
# Compiler item crane2410_config to establish crane2410: unconfig
@./mkconfig $(@:_config=) arm arm920t crane2410 NULL s3c24x0
The following meanings:
arm: CPU architecture (ARCH)
arm920t: Type (CPU) CPU, which corresponds to a cpu / arm920t subdirectory. crane2410: model development board (BOARD), corresponding to a board / crane2410 directory. NULL: Developer / or distributor (vender).
s3c24x0: system on chip (SOC).
In the board established subdirectory crane2410
[uboot@localhost uboot]#cp rf board/smdk2410 board/crane2410 [uboot@localhost uboot]#cd board/crane2410
[uboot@localhost crane2410]#mv smdk2410.c crane2410.c
In the include / configs / build configuration header
[uboot@localhost crane2410]#cd ../..
[uboot@localhost uboot]#cp include/configs/smdk2410.h include/configs/crane2410.h
Specify the path of cross compiler tool
[uboot@localhost uboot]#vi ~/.bashrc
export PATH=/usr/local/arm/2.95.3/bin:$PATH
Compile test success
[uboot@localhost uboot]#make crane2410_config [uboot@localhost uboot]#make CROSS_COMPILE=armlinux
3.2.6 modify lowlevel_init.S file
In accordance with the configuration of the memory area of the development board, modification board / crane2410 / lowlevel_init.S file, my changes are as follows:
#include <config.h>
#include <version.h>
#define BWSCON 0x48000000
/* BWSCON */
#define DW8 (0x0)
#define DW16 (0x1)
#define DW32 (0x2)
#define WAIT (0x1<<2)
#define UBLB (0x1<<3)
#define B1_BWSCON (DW16)
#define B2_BWSCON (DW16)
#define B3_BWSCON (DW16 + WAIT + UBLB)
#define B4_BWSCON (DW16)
#define B5_BWSCON (DW16)
#define B6_BWSCON (DW32)
#define B7_BWSCON (DW32)
/* BANK0CON */
#define B0_Tacs 0x3 /* 0clk */
#define B0_Tcos 0x3 /* 0clk */
#define B0_Tacc 0x7 /* 14clk */
#define B0_Tcoh 0x3 /* 0clk */
#define B0_Tah 0x3 /* 0clk */
#define B0_Tacp 0x3
#define B0_PMC 0x3 /* normal */
/* BANK1CON */
#define B1_Tacs 0x3 /* 0clk */
#define B1_Tcos 0x3 /* 0clk */
#define B1_Tacc 0x7 /* 14clk */
#define B1_Tcoh 0x3 /* 0clk */
#define B1_Tah 0x3 /* 0clk */
#define B1_Tacp 0x3
#define B1_PMC 0x0
#define B2_Tacs 0x0
#define B2_Tcos 0x0
#define B2_Tacc 0x7
#define B2_Tcoh 0x0
#define B2_Tah 0x0
| #define #define |
B2_Tacp B2_PMC |
0x0 0x0 |
|
||||
| #define |
B3_Tacs |
0x0 |
/* |
0clk |
*/ |
||
| #define |
B3_Tcos |
0x3 |
/* |
4clk |
*/ |
||
| #define |
B3_Tacc |
0x7 |
/* |
14clk |
*/ |
||
| #define |
B3_Tcoh |
0x1 |
/* |
1clk |
*/ |
||
| #define |
B3_Tah |
0x0 |
/* |
0clk |
*/ |
||
| #define |
B3_Tacp |
0x3 |
/* |
6clk |
*/ |
||
| #define |
B3_PMC |
0x0 |
/* |
normal |
*/ |
||
| #define |
B4_Tacs |
0x0 |
/* |
0clk |
*/ |
||
| #define |
B4_Tcos |
0x0 |
/* |
0clk |
*/ |
||
| #define |
B4_Tacc |
0x7 |
/* |
14clk |
*/ |
||
| #define |
B4_Tcoh |
0x0 |
/* |
0clk |
*/ |
||
| #define #define #define |
B4_Tah B4_Tacp B4_PMC |
0x0 0x0 0x0 |
/*
/* |
0clk
normal |
*/
*/ |
||
| #define |
B5_Tacs |
0x0 |
/* |
0clk |
*/ |
||
| #define |
B5_Tcos |
0x0 |
/* |
0clk |
*/ |
||
| #define |
B5_Tacc |
0x7 |
/* |
14clk |
*/ |
||
| #define |
B5_Tcoh |
0x0 |
/* |
0clk |
*/ |
||
| #define #define #define |
B5_Tah B5_Tacp B5_PMC |
0x0 0x0 0x0 |
/*
/* |
0clk
normal |
*/
*/ |
||
| #define #define |
B6_MT B6_Trcd |
0x3 0x1 |
/* |
SDRAM |
*/ |
||
| #define B6_SCAN |
|
0x1 |
/* |
9bit */ |
|
||
| #define B7_MT #define B7_Trcd #define B7_SCAN |
|
0x3 0x1 0x1 |
/* /* /* |
SDRAM */ 3clk */ 9bit */ |
|
||
| /* REFRESH parameter #define REFEN |
*/ |
0x1 |
/* |
Refresh enable |
*/ |
||
| #define TREFMD #define Trp #define Trc #define Tchr #define REFCNT |
|
0x0 0x0 0x3 0x2 1113 |
/* /* /* /* /* |
CBR(CAS before 2clk */ 7clk */ 3clk */ period=15.6us, |
RAS)/Auto refresh */
HCLK=60Mhz, (2048+1-15.6*60) */ |
||
/**************************************/
_TEXT_BASE:
.word TEXT_BASE
.globl lowlevel_init lowlevel_init:
/* memory control configuration */
/* make r0 relative the current location so that it */
/* reads SMRDATA out of FLASH rather than memory ! */ ldr r0, =SMRDATA
ldr r1, _TEXT_BASE sub r0, r0, r1
ldr r1, =BWSCON /* Bus Width Status Controller */ add r2, r0, #13*4
0:
ldr r3, [r0], #4
str r3, [r1], #4
cmp r2, r0
bne 0b
/* everything is fine now */ mov pc, lr
.ltorg
/* the literal pools origin */
SMRDATA:
.word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+( B7_BWSCON<<28))
.word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
.word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
.word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
.word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
.word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
.word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
.word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
.word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
.word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
.word 0x31
.word 0x30
.word 0x30
UBOOT 的 Nand Flash 移植
UBOOT 的 Nand Flash 支持见第七部分的第 3 节.
重新编译 u-boot
[uboot@localhost uboot1.1.4]make CROSS_COMPILE=armlinux
把 u-boot 烧入 flash
1. 通过仿真器烧入 uboot
通过仿真器 uboot 烧写到 flash 中就可以从 NAND flash 启动了. 2. 通过 JTAG 接口，由工具烧入 flash