Storage System Overview
A memory system including a main memory and secondary memory.
Classification: a random access memory RAM (Random Access Memory), stores information easily lost;
A read only memory ROM (Read Only Memory), the stored information is not lost.
Specifications memory: capacity, speed and parity prices.
= The number of the storage capacity of the storage unit stores word length * (memory capacity refers to the total memory can store binary information)
Memory speed: access time, data transfer rate and the memory cycle
Access time Ta: refers to initiate a memory operation from beginning to completion of the operation time experienced.
Memory cycle Tm: refers to the minimum time between two consecutive starts a separate memory required for the operation.
Data transfer rate Bm: i.e. bandwidth refers to the read / write memory in a unit of time the number of bits. Unit: bit / s, or B / s
Easier to make highly integrated DRAM main memory chips must be refreshed regularly, to avoid the loss of stored data.
Specified dynamic refresh of the storage capacitor to "1" again to supplement the electric charge leaks out along the leakage path.
Refresh in three ways:
A, concentrated refresh mode access speed, the "dead zone"
B, refresh mode dispersion no "dead zone", a longer access cycle system
C, asynchronous refresh mode practical
Second, the main memory capacity is extended:
Extended word, bit extension, word-bit extensions.
A main memory connected with the CPU, to complete the connection address lines, data lines and control lines, also relates to a chip select decode the like between the chips.
Exam focus: the expansion memory connection
Bit extension connection: the address lines of all chips, chip select lines, read lines respectively in parallel with, the data lines are drawn.
Extended word connection: the address lines of all chips, data lines, read lines respectively connected to the CPU bus, each chip of the chip select lines are connected to the decoder to use a high level after the address decoding in parallel.
Brush exercises! Brush exercises! Brush exercises!
Main memory connected with the CPU via the main connection includes three sets: the address bus (AB), a data bus (DB) and a control bus (CB), collectively referred to as the system bus.
Memory address register (MAR) can receive the program counter (PC) instruction address or operand address from the arithmetic unit to determine a cell to be accessed.
The memory data register (MDR) is a buffer member main memory or write data to the read data from main memory.
Third, to be continued