FPGA doubt the rising edge detection

always @ (posedge clk_a or negedge rst_n)
    begin
        if (rst_n == 1'b0) 
            begin
               pules_a_r1 <= 1'b0;
               pules_a_r2 <= 1'b0;
               pules_a_r3 <= 1'b0;
            end
        else 
            begin                                   //打3拍
               pules_a_r1 <= pulse_b;
               pules_a_r2 <= pules_a_r1;
               pules_a_r3 <= pules_a_r2;
            End 
    End 

ASSIGN pulse_a_pos   = (~ pules_a_r3) & pules_a_r2;    // rising edge detection

= & pulse_a_neg pules_a_r3 ASSIGN (~ pules_a_r2);    // falling edge detection 
assign pulse_a = pules_a_r2;

In pulse_b, pules_a_r1, pules_a_r2, pules_a_r3 these signals, pulse_b is up to date, and pules_a_r1, pules_a_r2, pules_a_r3 this access is the last state pulse_b of the last state, on the last state.

Therefore, the rising edge detection pules_a_r2 & (~ pules_a_r3); in,  pules_a_r3 is a state of pules_a_r3, the state is 0, then the state is 1, 0 to 1, the rising edge detection!

always @ (posedge clk_a ornegedge rst_n) beginif (rst_n == 1'b0) begin pules_a_r1 <= 1'b0; pules_a_r2 <= 1'b0; pules_a_r3 <= 1'b0; endelsebegin//打3拍 pules_a_r1 <= pulse_b; pules_a_r2 <= pules_a_r1; pules_a_r3 <= pules_a_r2; endendassign pulse_a_pos = pules_a_r2 & (~pules_a_r3); //上升沿检测assign pulse_a_neg = pules_a_r3 & (~pules_a_r2); //下降沿检测assign pulse_a = pules_a_r2;