pci-e gen2 x4 link slots meaning_English

PCI  Express is the next generation bus interface. In 2001, Intel company proposed the new generation to replace the PCI bus, called the third generation I / O bus technology. Then in 2002 Intel, AMD, DELL, IBM, including industry-leading companies to complete the drafting of specifications of new technology, named as PCI  Express . It uses the current popular industry point serial connection than PCI parallel architecture and share earlier computer bus, each device has its own dedicated connection, does not need to request the entire bus bandwidth, but also the data transfer rate raised to a very high frequency, to achieve high bandwidth PCI can not provide.
PCI Express bus interface depending on the bit width vary, including X1, X4, X8 and X16 (X2 mode for the internal interface rather than the slot mode). Short PCI Express card can be inserted into the PCI Express slot longer use. Substituted for AGP interface PCI Express interface bit width of X16.
The first generation of PCI Express 1.0 released in 2002, it works with high-speed serial interface transfer rate reached 2. 5GHz , Express and PCI  2.0 at 1.0 basis goes a step further, to enhance the interface speed to 5GHz . E-PCI  3.0 standard final plan completed in 2010-E and PCI  2.0 compared to, E-PCI  3.0Bandwidth continues to double to 10GB / s, in addition to a substantial increase in data throughput brought double the bandwidth, the PCI-E  3.0 signal speeds faster data transmission delay accordingly will be lower.
These are the PCI-E and the origins of some of the technical parameters.
Come back to your question gen2 x4 link becomes clear.
Express gen2 is to use the PCI  2.0 standard interface (socket),
X4 is the data bus width of the slot 4, link of course (interface) is connected.
Together it is to use the slot PCI Express 2.0 specification, data bus width of the interface 4.