Internal peripheral system control unit WDT

The internal control unit MCU peripherals recording three systems: WDT, Timer and RTC

1 WDT

1.1 Definitions

　　WDT: whatch dog timer. How to prove if the system is functioning properly, a certain amount of time to perform every piece of code can be, if that code is not executed, then that code or system died. It can be understood, the code is to perform a dog, it's the law, is to feed the dog's behavior to that part of the implementation of the law, if a period of time not to feed the dog died, the system will die. So, WDT is used to monitor whether the normal operation of the system, if the system is running out, the dog died, WDT is reset once the system.

FIG: WATCHDOG position in the MCU

As can be seen from the figure, WDT RESET are: BVICRESETn, CM3Core and System Components (matrix interconnection bus and memory protection unit MPU), but will not reset the WDT system debug module.

1.2 Circuit Design

　　FRC: Free Running Counter, which is a 32-bit counter is decremented by one.

FIG: Timer block diagram showing a structure of

FIG: register reference distribution

WDOGLOAD register: storing an initial value, after a continued decrease the minimum value is 1;

WDOGVALUE register: a reporting effect, indicating the current value;

WDOGCONTROL Register: This register control software to control some of the functional components of the watchdog

Related register setting, the MCU can find a register manual, which can substantially be used as a reference SPEC.

Design difficulties across clock domains 2 WDT's

//------------------------------------------------------------------------------
// Load enable register
//------------------------------------------------------------------------------
// The load_en pulse needs to be sampled into the WDOGCLK domain even if PCLK
// is subsequently disabled.

  // load_req_tog_p is toggled if a new load request is received and there are no
  //  pending load requests. This prevents multiple toggles before the next
  //  WDOGCLK edge.
  assign load_tog_en = load_en_reg & (~load_req_w); // New load request and none pending

  // load_tog_en high toggles LoadReqTog on next PCLK
  always @ (negedge PRESETn or posedge PCLK)
    begin : p_load_req_tog_p_seq
      if (~PRESETn)
        load_req_tog_p <= 1'b0;
      else
        if (load_tog_en)
          load_req_tog_p <= (~load_req_tog_p);
    end

  // Register LoadReqTog into WDOGCLK domain
  always @(negedge WDOGRESn or posedge WDOGCLK)
  begin : p_load_req_tog_w_seq
    if (~WDOGRESn)
      load_req_tog_w <= 1'b0;
    else
      if (WDOGCLKEN)
        load_req_tog_w <= load_req_tog_p;
  end

  // load_req_w goes high on the PCLK edge after load_tog_en and low on the next
  //  valid WDOGCLK edge
  assign load_req_w = load_req_tog_p ^ load_req_tog_w;