Sequential Consistency Definition
Precise definition of Sequential Consistency comes from Leslie Lamport brother (later we'll mention him several times).
He was originally defined consistency model based on shared memory multi-CPU parallel computing, but can also be extended to a distributed system, in fact, multi-CPU parallel computing can also be regarded as a distributed system.
The model is defined
the result of any execution is the same as if the operations of all the processors were executed in some sequential order, and the operations of each individual processor appear in this sequence in the order specified by its program
Into a distributed system, meaning that no matter how the system is running, the results obtained if all the operations of all nodes run in sequential order after a sort, but in this sequential order sequence, operating from the same node remains the order they are specified in the node.
Sequential Consistency examples
Leslie Lamport brother saying consistently read awkwardly us look at a few examples. FIG physical time from left to right represents, W (a) represents write data a, R (a) denotes the read data a.
It can be seen that the two systems are not perfect, but their model can be seen as Sequential Consistency, because by transformation, can always be justified, that meet the definition can be found in sequential order.
Sequential Consistency and hardware
也许有人会问，同一个进程中保留操作顺序不是显而易见的么?实际上随着硬件技术，尤其是多核、多CPU技术的发展，一个CPU核心运行的进程，不一定能观测到另一个核心进程的操作顺序。
在论文中，Leslie Lamport老哥举了这样一个例子，有一个互斥算法，要求两个进程不能同时执行临界区方法，a和b两个变量初始值为0。正常情况下，最多一个进程执行临界区方法。
进程1执行序列如下：
a = 1
if (b!=0){
临界区方法
}
进程2执行序列如下：
b = 1
if (a!=0){
临界区方法
}
这个程序在多核CPU机器上运行时，有可能两个进程同时进入临界区。为什么呢?
我们先看一下现代CPU的架构
CPU一般具有多个核心，每个核心都有自己的L1 cache和L2 cache，cache之上还有Load Buffer和Store Buffer。写入时，处理器很有可能仅仅将数据写入Store Buffer，稍后再将Store Buffer中的数据统一写回cache，有可能再过一会儿才将cache的数据写回内存。同样，一个核心读取的数据说不定也已经被另一个核心修改过，只是它不知道而已。
所以上述进程对a和b的赋值，很有可能没被对方感知。
为了保证Sequential Consistency，Leslie Lamport老哥在论文中提出了两个要求:
Each processor issues memory requests in the order specified by its program
Memory requests from all processors issued to an individual memory module are serviced from a single FIFO queue. Issuing a memory request consists of entering the request on this queue.
But if they meet Sequential Consistency at the hardware level, will certainly be greatly reduced efficiency, it is generally these jobs will be to the upper layer of software developers do.